Searched refs:ExtendKind (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h821 ISD::NodeType ExtendKind) const;
H A DX86ISelLowering.cpp1616 ISD::NodeType ExtendKind) const {
1619 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp323 /// integers, ExtendKind can be used to specify how to generate the extra bits.
327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
1202 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; local
1206 ExtendKind = ISD::SIGN_EXTEND;
1208 ExtendKind = ISD::ZERO_EXTEND;
1210 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1211 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1218 &Parts[0], NumParts, PartVT, ExtendKind);
1226 if (ExtendKind
6425 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; local
[all...]
H A DTargetLowering.cpp1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; local
1016 ExtendKind = ISD::SIGN_EXTEND;
1018 ExtendKind = ISD::ZERO_EXTEND;
1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {

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