/external/llvm/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 31 virtual bool isBranch(const MCInst &Inst) const { 32 return Info->get(Inst.getOpcode()).isBranch(); 35 virtual bool isConditionalBranch(const MCInst &Inst) const { 36 return Info->get(Inst.getOpcode()).isConditionalBranch(); 39 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 43 virtual bool isIndirectBranch(const MCInst &Inst) const { 44 return Info->get(Inst.getOpcode()).isIndirectBranch(); 47 virtual bool isCall(const MCInst &Inst) const { 48 return Info->get(Inst [all...] |
H A D | MCCodeEmitter.h | 30 /// EncodeInstruction - Encode the given \arg Inst to bytes on the output 32 virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
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/external/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 13 uint64_t MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 15 if (Inst.getNumOperands() == 0 || 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 19 int64_t Imm = Inst.getOperand(0).getImm();
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H A D | MCObjectStreamer.cpp | 162 void MCObjectStreamer::EmitInstruction(const MCInst &Inst) { argument 164 for (unsigned i = Inst.getNumOperands(); i--; ) 165 if (Inst.getOperand(i).isExpr()) 166 AddValueSymbols(Inst.getOperand(i).getExpr()); 175 if (!getAssembler().getBackend().mayNeedRelaxation(Inst)) { 176 EmitInstToData(Inst); 184 getAssembler().getBackend().relaxInstruction(Inst, Relaxed); 192 EmitInstToFragment(Inst); 195 void MCObjectStreamer::EmitInstToFragment(const MCInst &Inst) { argument 196 MCInstFragment *IF = new MCInstFragment(Inst, getCurrentSectionDat [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 49 Instruction *Inst; member in struct:__anon7763::SimpleValue 51 SimpleValue(Instruction *I) : Inst(I) { 52 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!"); 56 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() || 57 Inst == DenseMapInfo<Instruction*>::getTombstoneKey(); 60 static bool canHandle(Instruction *Inst) { argument 62 if (CallInst *CI = dyn_cast<CallInst>(Inst)) 64 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || 65 isa<GetElementPtrInst>(Inst) || is 92 Instruction *Inst = Val.Inst; local 142 Instruction *Inst; member in struct:__anon7764::CallValue 153 canHandle(Instruction *Inst) argument 184 Instruction *Inst = Val.Inst; local 374 Instruction *Inst = I++; local 479 << *Inst << '\\n'); local [all...] |
H A D | Sink.cpp | 57 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const; 72 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument 78 for (Value::use_iterator I = Inst->use_begin(), 79 E = Inst->use_end(); I != E; ++I) { 135 Instruction *Inst = I; // The instruction to sink. local 143 if (isa<DbgInfoIntrinsic>(Inst)) 146 if (SinkInstruction(Inst, Stores)) 155 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument 158 if (Inst->mayWriteToMemory()) { 159 Stores.insert(Inst); 179 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument [all...] |
/external/llvm/lib/MC/MCDisassembler/ |
H A D | EDOperand.cpp | 28 Inst(inst), 129 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex]; 142 result = Inst.Inst->getOperand(MCOpIndex).getImm(); 146 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg(); 151 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm(); 166 unsigned baseReg = Inst.Inst [all...] |
/external/clang/test/Parser/ |
H A D | cxx-default-args.cpp | 10 typedef struct Inst { struct
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/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 105 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 107 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 110 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 112 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 114 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 116 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 118 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 120 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 126 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigne 862 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 873 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 885 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 892 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 922 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 939 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 960 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 970 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 978 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 993 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1013 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1034 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1046 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1060 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1069 DecodeSOImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1078 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1115 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1150 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1185 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1202 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1219 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1240 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1385 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1488 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1529 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1720 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1749 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1834 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1874 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1914 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1938 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1964 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1992 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2012 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2031 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2037 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2052 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2078 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2095 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2369 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2640 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2685 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2733 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2768 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2821 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2866 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2885 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2891 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2897 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2903 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2909 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2945 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 2969 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2977 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2985 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2993 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3008 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3022 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3032 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3040 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3057 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3112 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3121 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3136 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument 3151 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3164 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3195 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3225 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3240 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3251 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3276 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3287 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3300 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3309 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3319 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3335 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3377 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3409 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3417 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3425 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3445 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3452 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3475 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3502 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3527 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3555 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3580 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3605 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3664 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3722 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3789 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3853 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3923 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3987 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4061 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4126 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4152 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4178 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4205 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4242 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4276 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument 4291 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 4302 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4329 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4357 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4385 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4412 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/tools/llvm-objdump/ |
H A D | MCFunction.cpp | 55 MCInst Inst; local 56 if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())){ 57 Instructions.push_back(MCDecodedInst(Index, Size, Inst)); 58 if (Ana->isBranch(Inst)) { 59 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 72 } else if (Ana->isReturn(Inst)) { 76 } else if (Ana->isCall(Inst)) { 77 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 116 const MCDecodedInst &Inst = BB.getInsts().back(); local 118 if (Ana->isBranch(Inst [all...] |
H A D | MCFunction.h | 35 MCInst Inst; member in struct:llvm::MCDecodedInst 38 MCDecodedInst(uint64_t Address, uint64_t Size, MCInst Inst) argument 39 : Address(Address), Size(Size), Inst(Inst) {} 61 void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); } argument
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/external/llvm/utils/TableGen/ |
H A D | InstrInfoEmitter.cpp | 54 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument 57 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 66 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 70 OperandList.push_back(Inst.Operands[i]); 72 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 73 OperandList.push_back(Inst.Operands[i]); 103 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) 108 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) 113 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type."); 114 Res += Inst 188 Record *Inst = (*II)->TheDef; local 280 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument [all...] |
H A D | InstrInfoEmitter.h | 45 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 57 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 184 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 186 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 188 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 190 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 192 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 194 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 196 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 198 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 200 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 202 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigne 1382 addExpr(MCInst &Inst, const MCExpr *Expr) const argument 1392 addCondCodeOperands(MCInst &Inst, unsigned N) const argument 1399 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument 1404 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument 1409 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument 1414 addITMaskOperands(MCInst &Inst, unsigned N) const argument 1419 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument 1424 addCCOutOperands(MCInst &Inst, unsigned N) const argument 1429 addRegOperands(MCInst &Inst, unsigned N) const argument 1434 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument 1444 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument 1453 addShifterImmOperands(MCInst &Inst, unsigned N) const argument 1459 addRegListOperands(MCInst &Inst, unsigned N) const argument 1467 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument 1471 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument 1475 addRotImmOperands(MCInst &Inst, unsigned N) const argument 1481 addBitfieldOperands(MCInst &Inst, unsigned N) const argument 1492 addImmOperands(MCInst &Inst, unsigned N) const argument 1497 addFBits16Operands(MCInst &Inst, unsigned N) const argument 1503 addFBits32Operands(MCInst &Inst, unsigned N) const argument 1509 addFPImmOperands(MCInst &Inst, unsigned N) const argument 1516 addImm8s4Operands(MCInst &Inst, unsigned N) const argument 1524 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument 1532 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument 1540 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument 1548 addImm1_16Operands(MCInst &Inst, unsigned N) const argument 1556 addImm1_32Operands(MCInst &Inst, unsigned N) const argument 1564 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument 1573 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument 1582 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument 1590 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument 1598 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument 1606 addARMSOImmNotOperands(MCInst &Inst, unsigned N) const argument 1614 addARMSOImmNegOperands(MCInst &Inst, unsigned N) const argument 1622 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument 1627 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument 1632 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument 1640 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument 1646 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument 1864 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument 1871 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument 1878 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument 1885 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument 1896 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument 1908 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument 1914 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument 1925 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument 1930 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument 1935 addVecListOperands(MCInst &Inst, unsigned N) const argument 1940 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument 1946 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument 1951 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument 1956 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument 1961 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument 1969 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument 1981 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument 1995 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument 2009 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument 2023 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument 3796 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3814 cvtT2StrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3832 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3848 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3862 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3878 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3895 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3909 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3923 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3937 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3956 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3975 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3994 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4013 cvtLdrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4031 cvtStrdPre(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4049 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4063 cvtThumbMultiply(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4093 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4107 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4123 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4137 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5137 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument 5153 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument 5174 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5580 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 7238 checkTargetMatchPredicate(MCInst &Inst) argument 7284 MCInst Inst; local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.h | 19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate 21 Inst(unsigned Opc, unsigned ImmOpnd); 23 typedef SmallVector<Inst, 7 > InstSeq; 33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
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H A D | MipsRegisterInfo.cpp | 233 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 240 if (Inst->Opc == LUi) 242 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 244 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 245 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 248 for (++Inst; Inst != Seq.end() - 1; ++Inst) 249 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 250 .addImm(SignExtend64<16>(Inst [all...] |
/external/llvm/lib/Analysis/ |
H A D | PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) { argument 26 if (isa<PHINode>(Inst) || 27 isa<GetElementPtrInst>(Inst)) 30 if (isa<CastInst>(Inst) && 31 isSafeToSpeculativelyExecute(Inst)) 34 if (Inst->getOpcode() == Instruction::Add && 35 isa<ConstantInt>(Inst->getOperand(1))) 116 Instruction *Inst = dyn_cast<Instruction>(Addr); local 117 return Inst == 0 || CanPHITrans(Inst); 147 Instruction *Inst = dyn_cast<Instruction>(V); local [all...] |
H A D | MemDepPrinter.cpp | 102 Instruction *Inst = &*I; local 104 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory()) 107 MemDepResult Res = MDA.getDependency(Inst); 109 Deps[Inst].insert(std::make_pair(getInstTypePair(Res), 111 } else if (CallSite CS = cast<Value>(Inst)) { 115 DepSet &InstDeps = Deps[Inst]; 123 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) { 126 Deps[Inst].insert(std::make_pair(getInstTypePair(0, Unknown), 132 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 162 const Instruction *Inst = &*I; local [all...] |
H A D | MemoryDependenceAnalysis.cpp | 102 /// 'Inst's set in ReverseMap. If the set becomes empty, remove Inst's entry. 106 Instruction *Inst, KeyTy Val) { 108 InstIt = ReverseMap.find(Inst); 121 AliasAnalysis::ModRefResult GetLocation(const Instruction *Inst, argument 124 if (const LoadInst *LI = dyn_cast<LoadInst>(Inst)) { 136 if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 148 if (const VAArgInst *V = dyn_cast<VAArgInst>(Inst)) { 153 if (const CallInst *CI = isFreeCall(Inst)) { 159 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst)) 104 RemoveFromReverseMap(DenseMap<Instruction*, SmallPtrSet<KeyTy, 4> > &ReverseMap, Instruction *Inst, KeyTy Val) argument 378 getModRefInfo(const Instruction *Inst, const AliasAnalysis::Location &MemLoc) argument [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 149 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, 154 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, 159 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 164 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 169 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 174 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 179 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 184 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, 189 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 194 static DecodeStatus DecodeBC1(MCInst &Inst, 365 DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 377 DecodeCPURegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 388 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 399 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 410 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 418 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 437 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 453 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 464 DecodeCondCode(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 473 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 484 DecodeHWRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 495 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 505 DecodeBC1(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 515 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 526 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 534 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 545 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeAsmBackend.cpp | 53 bool mayNeedRelaxation(const MCInst &Inst) const; 60 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 78 bool MBlazeAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 79 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode()) 83 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) 84 hasExprOrImm |= Inst.getOperand(i).isExpr(); 101 void MBlazeAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { argument 102 Res = Inst; 103 Res.setOpcode(getRelaxedOpcode(Inst [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 61 bool processInstruction(MCInst &Inst, 341 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument 344 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 346 Inst.addOperand(MCOperand::CreateExpr(Expr)); 349 void addRegOperands(MCInst &Inst, unsigned N) const { argument 351 Inst.addOperand(MCOperand::CreateReg(getReg())); 354 void addImmOperands(MCInst &Inst, unsigned N) const { argument 356 addExpr(Inst, getImm()); 359 void addMem8Operands(MCInst &Inst, unsigned N) const { argument 360 addMemOperands(Inst, 362 addMem16Operands(MCInst &Inst, unsigned N) const argument 365 addMem32Operands(MCInst &Inst, unsigned N) const argument 368 addMem64Operands(MCInst &Inst, unsigned N) const argument 371 addMem80Operands(MCInst &Inst, unsigned N) const argument 374 addMem128Operands(MCInst &Inst, unsigned N) const argument 377 addMem256Operands(MCInst &Inst, unsigned N) const argument 381 addMemOperands(MCInst &Inst, unsigned N) const argument 390 addAbsMemOperands(MCInst &Inst, unsigned N) const argument 1237 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Ops) argument 1491 MCInst Inst; local 1514 MCInst Inst; local [all...] |
/external/regex-re2/re2/ |
H A D | prog.cc | 15 // Constructors per Inst opcode 17 void Prog::Inst::InitAlt(uint32 out, uint32 out1) { 23 void Prog::Inst::InitByteRange(int lo, int hi, int foldcase, uint32 out) { 31 void Prog::Inst::InitCapture(int cap, uint32 out) { 37 void Prog::Inst::InitEmptyWidth(EmptyOp empty, uint32 out) { 43 void Prog::Inst::InitMatch(int32 id) { 49 void Prog::Inst::InitNop(uint32 out) { 54 void Prog::Inst::InitFail() { 59 string Prog::Inst::Dump() { 139 Prog::Inst* i [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | LCSSA.cpp | 75 bool ProcessInstruction(Instruction *Inst, 178 bool LCSSA::ProcessInstruction(Instruction *Inst, argument 182 BasicBlock *InstBB = Inst->getParent(); 184 for (Value::use_iterator UI = Inst->use_begin(), E = Inst->use_end(); 204 BasicBlock *DomBB = Inst->getParent(); 205 if (InvokeInst *Inv = dyn_cast<InvokeInst>(Inst)) 213 SSAUpdate.Initialize(Inst->getType(), Inst->getName()); 225 PHINode *PN = PHINode::Create(Inst [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 180 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 182 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 184 return MCInstrAnalysis::isUnconditionalBranch(Inst); 187 virtual bool isConditionalBranch(const MCInst &Inst) const { 189 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 191 return MCInstrAnalysis::isConditionalBranch(Inst); 194 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 197 if (Info->get(Inst [all...] |