/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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H A D | SPUInstrInfo.cpp | 360 MachineInstrBuilder MIB; local 368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel); 374 MIB = BuildMI(&MBB, DL, get(SPU::BR)); 375 MIB.addMBB(TBB); 378 DEBUG((*MIB).dump()); 382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA)); 383 MIB.addSym(branchLabel); 384 MIB.addMBB(TBB); 388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); 389 MIB [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 98 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument 99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); 107 addRegOffset(const MachineInstrBuilder &MIB, argument 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument 117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 122 addFullAddress(const MachineInstrBuilder &MIB, argument 127 MIB 148 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument 174 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument [all...] |
H A D | X86InstrInfo.cpp | 1582 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), local 1589 MIB.addReg(0).addImm(1 << ShAmt) 1595 addRegOffset(MIB, leaInReg, true, 1); 1599 addRegOffset(MIB, leaInReg, true, -1); 1605 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1616 addRegReg(MIB, leaInReg, true, leaInReg, false); 1621 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1623 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1626 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1634 MachineInstr *NewMI = MIB; 2599 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); local 2633 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); local 2684 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); local 2744 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); local [all...] |
H A D | X86FastISel.cpp | 1792 MachineInstrBuilder MIB; local 1800 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) 1834 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)); 1836 MIB.addExternalSymbol(MemIntName, OpFlags); 1838 MIB.addGlobalAddress(GV, 0, OpFlags); 1843 MIB.addReg(X86::EBX); 1846 MIB.addReg(X86::AL); 1850 MIB.addReg(RegArgs[i]); 1854 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv())); 1937 static_cast<MachineInstr *>(MIB) [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 400 MIB.addOperand(MI.getOperand(OpIdx++)); 403 MIB.addOperand(MI.getOperand(OpIdx++)); 404 MIB.addOperand(MI.getOperand(OpIdx++)); 407 MIB.addOperand(MI.getOperand(OpIdx++)); 417 MIB 448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local 499 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local 583 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); local 840 MachineInstrBuilder MIB = local 852 MachineInstrBuilder MIB = local 944 MachineInstrBuilder MIB = local 975 MachineInstrBuilder MIB = local 1007 MachineInstrBuilder MIB = local [all...] |
H A D | Thumb1FrameLowering.cpp | 280 MachineInstrBuilder MIB = local 283 AddDefaultPred(MIB); 284 MIB->copyImplicitOps(&*MBBI); 304 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); local 305 AddDefaultPred(MIB); 323 MIB.addReg(Reg, getKillRegState(isKill)); 325 MIB.setMIFlags(MachineInstr::FrameSetup); 343 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); local 344 AddDefaultPred(MIB); 354 (*MIB) [all...] |
H A D | Thumb1RegisterInfo.cpp | 129 MachineInstrBuilder MIB = local 132 MIB = AddDefaultT1CC(MIB); 134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 137 AddDefaultPred(MIB); 241 const MachineInstrBuilder MIB = 244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local 262 MIB 268 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local [all...] |
H A D | Thumb2SizeReduction.cpp | 455 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); local 457 MIB.addOperand(MI->getOperand(0)); 458 MIB.addOperand(MI->getOperand(1)); 461 MIB.addImm(OffsetImm / Scale); 466 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); 471 MIB.addOperand(MI->getOperand(OpNum)); 474 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 477 MIB.setMIFlags(MI->getFlags()); 479 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local 516 MachineInstrBuilder MIB 526 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); local 673 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local 695 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local 764 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local 802 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local [all...] |
H A D | ARMBaseInstrInfo.h | 302 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument 303 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 307 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument 308 return MIB.addReg(0); 312 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument 314 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 318 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument 319 return MIB.addReg(0);
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H A D | MLxExpansionPass.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) local 229 MIB.addImm(LaneImm); 230 MIB.addImm(Pred).addReg(PredReg); 232 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2) 237 MIB.addReg(TmpReg, getKillRegState(true)) 240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); 242 MIB.addImm(Pred).addReg(PredReg);
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H A D | ARMBaseInstrInfo.cpp | 675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); local 676 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 678 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679 AddDefaultPred(MIB); 732 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, argument 736 return MIB.addReg(Reg, State); 739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 740 return MIB.addReg(Reg, State, SubIdx); 808 MachineInstrBuilder MIB = local 812 MIB 822 MachineInstrBuilder MIB = local 952 MachineInstrBuilder MIB = local 968 MachineInstrBuilder MIB = local 1114 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) local 1182 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), local [all...] |
H A D | ARMFastISel.cpp | 219 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 221 const MachineInstrBuilder &MIB, 267 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { argument 268 MachineInstr *MI = &*MIB; 274 AddDefaultPred(MIB); 281 AddDefaultT1CC(MIB); 283 AddDefaultCC(MIB); 285 return MIB; 662 MachineInstrBuilder MIB; local 665 MIB 680 MachineInstrBuilder MIB; local 934 AddLoadStoreOperands(EVT VT, Address &Addr, const MachineInstrBuilder &MIB, unsigned Flags, bool useAM3) argument 1064 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local 1177 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local 1460 MachineInstrBuilder MIB; local 2493 MachineInstrBuilder MIB; local [all...] |
H A D | ARMFrameLowering.cpp | 216 MachineInstrBuilder MIB = local 220 AddDefaultCC(AddDefaultPred(MIB)); 435 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); local 437 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 441 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 446 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); 616 MachineInstrBuilder MIB = local 620 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 622 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), local 627 AddDefaultPred(MIB); 681 MachineInstrBuilder MIB = local 696 MachineInstrBuilder MIB = local 779 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) local [all...] |
H A D | Thumb2ITBlockPass.cpp | 185 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) local 193 MachineBasicBlock::iterator InsertPos = MIB; 236 MIB.addImm(Mask);
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H A D | ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); 779 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) local 786 MIB.addOperand(MI->getOperand(OpNum)); 789 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1084 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), local 1088 MIB.addImm(Offset).addImm(Pred).addReg(PredReg); 1090 MachineInstrBuilder MIB local 1748 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local 1762 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local [all...] |
H A D | Thumb2InstrInfo.cpp | 279 MachineInstrBuilder MIB = 284 AddDefaultCC(MIB); 411 MachineInstrBuilder MIB(&MI); 412 AddDefaultPred(MIB);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 159 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local 162 MIB.addReg(DestReg, RegState::Define); 165 MIB.addReg(ZeroReg); 168 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 239 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) local 241 return &*MIB; 382 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local 385 MIB.addReg(Cond[i].getReg()); 387 MIB.addMBB(TBB);
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/external/llvm/lib/CodeGen/ |
H A D | MachineInstrBundle.cpp | 109 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(), local 190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | 199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
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H A D | MachineSSAUpdater.cpp | 190 MachineInstrBuilder MIB(InsertedPHI); 192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 622 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 633 MIB.addReg(0U); // undef 635 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 641 MIB.addCImm(CI); 643 MIB.addImm(CI->getSExtValue()); 645 MIB.addFPImm(CF); 649 MIB.addReg(0U); 653 MIB.addReg(0U); 656 MIB [all...] |
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeFrameLowering.cpp | 59 MachineInstr::mop_iterator MIB = MBB->operands_begin(); local 62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) { 99 MachineBasicBlock::iterator MIB = MBB->begin(); local 121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) { 171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)) local 395 return &*MIB;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE)) local 123 return &*MIB;
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