Searched refs:OpNum (Results 1 - 22 of 22) sorted by relevance

/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.h39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
48 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
51 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
52 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
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H A DARMInstPrinter.cpp226 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, argument
228 const MCOperand &MO1 = MI->getOperand(OpNum);
242 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, argument
244 const MCOperand &MO1 = MI->getOperand(OpNum);
245 const MCOperand &MO2 = MI->getOperand(OpNum+1);
246 const MCOperand &MO3 = MI->getOperand(OpNum+2);
260 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, argument
262 const MCOperand &MO1 = MI->getOperand(OpNum);
263 const MCOperand &MO2 = MI->getOperand(OpNum+1);
369 unsigned OpNum,
368 printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
454 printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
472 printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
480 printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
488 printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
497 printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
504 printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
526 printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
539 printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
545 printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
555 printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
566 printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
572 printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
583 printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
592 printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
602 printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
612 printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
621 printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
627 printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
639 printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
691 printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
701 printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
708 printSBitModifierOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
717 printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
722 printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
727 printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
732 printCoprocOptionImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
737 printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
742 printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
747 printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
753 printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
830 printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
846 printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
66 const MachineOperand &MO = MI->getOperand(OpNum);
111 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument
113 const MachineOperand &Base = MI->getOperand(OpNum);
114 const MachineOperand &Disp = MI->getOperand(OpNum+1);
121 printOperand(MI, OpNum+1, O, "nohash");
126 printOperand(MI, OpNum, O);
/external/llvm/lib/Target/
H A DTargetInstrInfo.cpp30 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
32 if (OpNum >= MCID.getNumOperands())
35 short RegClass = MCID.OpInfo[OpNum].RegClass;
36 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.h57 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
60 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
63 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
H A DARMAsmPrinter.cpp323 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
325 const MachineOperand &MO = MI->getOperand(OpNum);
410 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
420 if (MI->getOperand(OpNum).isReg()) {
422 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
428 if (!MI->getOperand(OpNum).isImm())
430 O << MI->getOperand(OpNum).getImm();
434 printOperand(MI, OpNum, O);
440 if (MI->getOperand(OpNum).isReg()) {
441 unsigned Reg = MI->getOperand(OpNum)
531 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
927 int OpNum = 1; local
976 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; local
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H A DThumb2SizeReduction.cpp337 unsigned OpNum = 3; // First 'rest' of operands. local
375 OpNum = 4;
396 OpNum = 0;
405 OpNum = 2;
413 OpNum = 0;
420 OpNum = 2;
470 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
471 MIB.addOperand(MI->getOperand(OpNum));
H A DARMLoadStoreOptimizer.cpp785 for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum)
786 MIB.addOperand(MI->getOperand(OpNum));
H A DARMISelLowering.cpp4409 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4431 if (OpNum == OP_COPY) {
4442 switch (OpNum) {
4460 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4466 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4470 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4474 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4478 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
/external/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp2018 unsigned OpNum = 0; local
2020 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
2021 getValue(Record, OpNum, LHS->getType(), RHS) ||
2022 OpNum+1 > Record.size())
2025 int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType());
2029 if (OpNum < Record.size()) {
2034 if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
2036 if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
2042 if (Record[OpNum] & (1 << bitc::PEO_EXACT))
2049 unsigned OpNum local
2065 unsigned OpNum = 0; local
2087 unsigned OpNum = 0; local
2108 unsigned OpNum = 0; local
2133 unsigned OpNum = 0; local
2148 unsigned OpNum = 0; local
2173 unsigned OpNum = 0; local
2184 unsigned OpNum = 0; local
2197 unsigned OpNum = 0; local
2217 unsigned OpNum = 0; local
2241 unsigned OpNum = 0; local
2327 unsigned OpNum = 4; local
2452 unsigned OpNum = 0; local
2464 unsigned OpNum = 0; local
2485 unsigned OpNum = 0; local
2499 unsigned OpNum = 0; local
2522 unsigned OpNum = 0; local
2542 unsigned OpNum = 0; local
2582 unsigned OpNum = 2; local
[all...]
/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h148 int getOperandConstraint(unsigned OpNum, argument
150 if (OpNum < NumOperands &&
151 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
153 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp106 unsigned short OpNum; member in struct:Operator
112 : ShuffleMask(shufflemask), OpNum(opnum), Name(name), Cost(cost) {
394 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0;
395 assert(OpNum < 16 && "Too few bits to encode operation!");
402 unsigned Val = (CostSat << 30) | (OpNum << 26) | (LHS << 13) | RHS;
/external/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
H A DMipsAsmPrinter.cpp397 unsigned OpNum, unsigned AsmVariant,
403 const MachineOperand &MO = MI->getOperand(OpNum);
396 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp262 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
264 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
266 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
268 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1202 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, argument
1204 const MCOperand &MO1 = MI.getOperand(OpNum);
1205 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1206 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1220 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, argument
1222 const MCOperand &MO1 = MI.getOperand(OpNum);
1241 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups) const argument
1257 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups) const argument
[all...]
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h348 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
350 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
355 unsigned OpNum,
H A DX86InstrInfo.cpp2911 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument
2913 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
2934 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
2936 unsigned Reg = MI->getOperand(OpNum).getReg();
3154 unsigned OpNum = Ops[0]; local
3164 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3166 } else if (OpNum == 0) { // If operand 0
3175 } else if (OpNum == 1) {
3177 } else if (OpNum == 2) {
H A DX86ISelLowering.cpp4535 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4539 unsigned NumElems, unsigned &OpNum) {
4559 OpNum = SeenV1 ? 0 : 1;
4537 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument
/external/llvm/lib/CodeGen/
H A DRegAllocFast.cpp74 unsigned short LastOpNum; // OpNum on LastUse.
172 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
174 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
576 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, argument
601 LRI->LastOpNum = OpNum;
609 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, argument
616 MachineOperand &MO = MI->getOperand(OpNum);
652 LRI->LastOpNum = OpNum;
657 // setPhysReg - Change operand OpNum i
660 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument
[all...]
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h57 /// class constraint for OpNum, or NULL.
59 unsigned OpNum,
770 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
788 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument
795 /// before MI to eliminate an unwanted dependency on OpNum.
812 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp68 unsigned OpNum) {
69 unsigned SrcReg = MI.getOperand(OpNum).getReg();
70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
67 getVEXRegisterEncoding(const MCInst &MI, unsigned OpNum) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4168 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4185 if (OpNum == OP_COPY) {
4196 switch (OpNum) {

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