/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 88 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 91 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 92 MVT VT = Outs[i].VT; 93 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 102 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 105 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 106 MVT VT = Outs[i].VT; 107 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 120 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 122 unsigned NumOps = Outs [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 97 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 119 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 120 EVT VT = Outs[i].VT; 121 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 135 &Outs, 139 unsigned NumOps = Outs.size(); 150 EVT ArgVT = Outs[i].VT; 151 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 134 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
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H A D | HexagonISelLowering.h | 75 SmallVectorImpl<ISD::OutputArg> &Outs, 100 const SmallVectorImpl<ISD::OutputArg> &Outs, 122 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | HexagonCallingConvLower.h | 85 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 90 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | HexagonISelLowering.cpp | 291 const SmallVectorImpl<ISD::OutputArg> &Outs, 303 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 374 const SmallVectorImpl<ISD::OutputArg> &Outs, 380 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 406 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 408 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 417 Outs, OutVals, Ins, DAG); 445 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1459 const SmallVectorImpl<ISD::OutputArg> &Outs, 289 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 371 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1453 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument [all...] |
/external/llvm/lib/Target/PTX/ |
H A D | PTXISelLowering.h | 59 const SmallVectorImpl<ISD::OutputArg> &Outs, 67 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | PTXISelLowering.cpp | 293 const SmallVectorImpl<ISD::OutputArg> &Outs, 303 assert(Outs.size() == 0 && "Kernel must return void."); 306 assert(Outs.size() <= 1 && "Can at most return one value."); 318 assert(Outs.size() < 2 && "Device functions can return at most one value"); 320 if (Outs.size() == 1) { 330 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 331 EVT RegVT = Outs[i].VT; 387 const SmallVectorImpl<ISD::OutputArg> &Outs, 411 unsigned outSize = isPrintf ? 2 : Outs.size(); 414 // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Out 290 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 384 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.h | 81 const SmallVectorImpl<ISD::OutputArg> &Outs, 90 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | SparcISelLowering.cpp | 82 const SmallVectorImpl<ISD::OutputArg> &Outs, 96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 351 const SmallVectorImpl<ISD::OutputArg> &Outs, 363 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 375 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 376 ISD::ArgFlagsTy Flags = Outs[i].Flags; 409 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 80 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 348 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.h | 165 const SmallVectorImpl<ISD::OutputArg> &Outs, 174 const SmallVectorImpl<ISD::OutputArg> &Outs,
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.h | 138 const SmallVectorImpl<ISD::OutputArg> &Outs, 147 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | MBlazeISelLowering.cpp | 686 const SmallVectorImpl<ISD::OutputArg> &Outs, 706 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze); 1010 const SmallVectorImpl<ISD::OutputArg> &Outs, 1022 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze); 684 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1009 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 128 const SmallVectorImpl<ISD::OutputArg> &Outs, 157 const SmallVectorImpl<ISD::OutputArg> &Outs, 166 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | MSP430ISelLowering.cpp | 272 const SmallVectorImpl<ISD::OutputArg> &Outs, 286 Outs, OutVals, Ins, dl, DAG, InVals); 381 const SmallVectorImpl<ISD::OutputArg> &Outs, 389 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 397 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); 440 &Outs, 450 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); 269 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 379 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 436 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 120 const SmallVectorImpl<ISD::OutputArg> &Outs, 179 const SmallVectorImpl<ISD::OutputArg> &Outs, 188 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | XCoreISelLowering.cpp | 879 const SmallVectorImpl<ISD::OutputArg> &Outs, 895 Outs, OutVals, Ins, dl, DAG, InVals); 907 const SmallVectorImpl<ISD::OutputArg> &Outs, 922 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 1205 const SmallVectorImpl<ISD::OutputArg> &Outs, 1209 return CCInfo.CheckReturn(Outs, RetCC_XCore); 1215 const SmallVectorImpl<ISD::OutputArg> &Outs, 1228 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 876 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 904 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1203 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 1213 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 444 const SmallVectorImpl<ISD::OutputArg> &Outs, 453 const SmallVectorImpl<ISD::OutputArg> &Outs, 459 const SmallVectorImpl<ISD::OutputArg> &Outs, 479 const SmallVectorImpl<ISD::OutputArg> &Outs, 487 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | PPCISelLowering.cpp | 2245 &Outs, 2252 unsigned NumOps = Outs.size(); 2263 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2264 EVT ArgVT = Outs[i].VT; 2870 const SmallVectorImpl<ISD::OutputArg> &Outs, 2881 isTailCall, Outs, OutVals, Ins, 2885 isTailCall, Outs, OutVals, Ins, 2893 const SmallVectorImpl<ISD::OutputArg> &Outs, 2933 unsigned NumArgs = Outs.size(); 2936 MVT ArgVT = Outs[ 2240 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument 2867 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2890 LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3099 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3469 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 3480 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 201 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 212 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 150 const SmallVectorImpl<ISD::OutputArg> &Outs, 159 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | MipsISelLowering.cpp | 2114 const SmallVectorImpl<ISD::OutputArg> &Outs) { 2115 unsigned NumOps = Outs.size(); 2117 MVT ArgVT = Outs[i].VT; 2118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2121 if (Outs[i].IsFixed) 2338 const SmallVectorImpl<ISD::OutputArg> &Outs, 2358 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2360 AnalyzeMips64CallOperands(CCInfo, Outs); 2362 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 2419 ISD::ArgFlagsTy Flags = Outs[ 2113 AnalyzeMips64CallOperands(CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs) argument 2335 LowerCall(SDValue InChain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2915 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 468 const SmallVectorImpl<ISD::OutputArg> &Outs, 485 const SmallVectorImpl<ISD::OutputArg> &Outs, 492 const SmallVectorImpl<ISD::OutputArg> &Outs,
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 704 const SmallVectorImpl<ISD::OutputArg> &Outs, 802 const SmallVectorImpl<ISD::OutputArg> &Outs, 811 const SmallVectorImpl<ISD::OutputArg> &Outs, 826 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | X86FastISel.cpp | 739 SmallVector<ISD::OutputArg, 4> Outs; local 741 Outs, TLI); 747 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 780 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 786 if (Outs[0].Flags.isSExt()) 791 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : 1550 SmallVector<ISD::OutputArg, 4> Outs; 1553 Outs, TLI, &Offsets); 1556 Outs, FT [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 68 SmallVector<ISD::OutputArg, 4> Outs; local 70 Fn->getAttributes().getRetAttributes(), Outs, TLI); 73 Outs, Fn->getContext());
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