Searched refs:Src2 (Results 1 - 3 of 3) sorted by relevance
/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \ 54 GenericValue Src2, Type *Ty) { 65 GenericValue Src2, Type *Ty) { 76 GenericValue Src2, Type *Ty) { 87 GenericValue Src2, Type *Ty) { 98 GenericValue Src2, Type *Ty) { 101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); 104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); 114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \ 124 (void*)(intptr_t)Src2 53 executeFAddInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 64 executeFSubInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 75 executeFMulInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 86 executeFDivInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 97 executeFRemInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 127 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument 140 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument 153 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1609 unsigned Src2 = MI->getOperand(2).getReg(); local 1613 if (Src == Src2) { 1625 .addReg(Src2, getKillRegState(isKill2)); 1629 LV->replaceKillInstruction(Src2, MI, InsMI2); 1854 unsigned Src2 = MI->getOperand(2).getReg(); local 1858 if (TargetRegisterInfo::isVirtualRegister(Src2) && 1859 !MF.getRegInfo().constrainRegClass(Src2, RC)) 1865 Src, isKill, Src2, isKill2); 1867 LV->replaceKillInstruction(Src2, MI, NewMI); 1875 unsigned Src2 local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 2819 SDValue Src2 = getValue(I.getOperand(1)); local 2830 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2841 // First check for Src1 in low and Src2 in high 2846 VT, Src1, Src2)); 2849 // Then check for Src2 in low and Src1 in high 2854 VT, Src2, Src1)); 2862 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2868 MOps2[0] = Src2; 2873 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2886 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, [all...] |
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