Searched refs:TARGET_PAGE_MASK (Results 1 - 25 of 29) sorted by relevance

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/external/qemu/
H A Dsoftmmu_template.h75 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
116 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
117 if (tlb_addr & ~TARGET_PAGE_MASK) {
124 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
168 env->tlb_table[mmu_idx][index].addr_read ^= TARGET_PAGE_MASK;
169 env->tlb_table[mmu_idx][index].addr_write ^= TARGET_PAGE_MASK;
172 env->tlb_table[mmu_idx][index + 1].addr_read ^= TARGET_PAGE_MASK;
173 env->tlb_table[mmu_idx][index + 1].addr_write ^= TARGET_PAGE_MASK;
204 if ((addr & TARGET_PAGE_MASK)
[all...]
H A Dexec.c203 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
280 page_set_flags(startaddr & TARGET_PAGE_MASK,
321 page_set_flags(addr & TARGET_PAGE_MASK,
682 address &= TARGET_PAGE_MASK;
791 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
888 tb_start = tb->pc & ~TARGET_PAGE_MASK;
894 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
933 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
935 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
985 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
[all...]
H A Dpoison.h33 #pragma GCC poison TARGET_PAGE_MASK
H A Dsoftmmu_header.h94 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
115 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
140 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
H A Dexec-all.h397 (addr & TARGET_PAGE_MASK))) {
400 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
H A Darch_init.c381 flags = addr & ~TARGET_PAGE_MASK;
382 addr &= TARGET_PAGE_MASK;
H A Dkqemu.c331 end = (start_addr + size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
332 start_addr &= TARGET_PAGE_MASK;
335 kphys_mem->ram_addr = phys_offset & TARGET_PAGE_MASK;
336 io_index = phys_offset & ~TARGET_PAGE_MASK;
H A Dcpu-all.h728 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) macro
729 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
H A Dkvm-all.c675 ram_addr_t flags = phys_offset & ~TARGET_PAGE_MASK;
679 if (start_addr & ~TARGET_PAGE_MASK) {
H A Dcpu-exec.c140 phys_page1 = phys_pc & TARGET_PAGE_MASK;
154 virt_page2 = (pc & TARGET_PAGE_MASK) +
/external/qemu/memcheck/
H A Dmemcheck_util.c189 if ((start & TARGET_PAGE_MASK) ==
190 (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
191 cpu_single_env->tlb_table[1][index].addr_write ^= TARGET_PAGE_MASK;
194 if ((start & TARGET_PAGE_MASK) ==
195 (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
196 cpu_single_env->tlb_table[1][index].addr_read ^= TARGET_PAGE_MASK;
H A Dmemcheck.c267 const target_ulong end_page = (addr + buf_size - 1) & TARGET_PAGE_MASK;
269 addr &= TARGET_PAGE_MASK;
/external/qemu/target-i386/
H A Dhax-darwin.c61 ram_addr_t flags = phys_offset & ~TARGET_PAGE_MASK;
67 if ( (start_addr & ~TARGET_PAGE_MASK) || (size & ~TARGET_PAGE_MASK))
H A Dhax-windows.c99 ram_addr_t flags = phys_offset & ~TARGET_PAGE_MASK;
108 if ( (start_addr & ~TARGET_PAGE_MASK) || (size & ~TARGET_PAGE_MASK))
H A Dhelper.c1000 virt_addr = addr & TARGET_PAGE_MASK;
1243 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1244 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1360 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1361 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
H A Dtranslate.c2293 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2294 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
/external/qemu/hw/
H A Dmips_r4k.c109 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
H A Darmv7m.c187 sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
H A Dgoldfish_pipe.c1016 uint32_t page = address & TARGET_PAGE_MASK;
1036 uint32_t page = address & TARGET_PAGE_MASK;
/external/qemu/target-mips/
H A Dhelper.c74 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
245 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
300 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
301 physical & TARGET_PAGE_MASK, prot,
620 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
H A Dop_helper.c1063 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1119 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1523 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1576 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1591 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1879 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1907 (addr & TARGET_PAGE_MASK), 0)) {
1925 if ((ptr & TARGET_PAGE_MASK) != page) {
1927 page = ptr & TARGET_PAGE_MASK;
[all...]
/external/qemu/target-arm/
H A Dtranslate-android.h157 const target_ulong phys_page1 = phys_pc & TARGET_PAGE_MASK;
/external/qemu/tcg/x86_64/
H A Dtcg-target.c590 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
785 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
/external/qemu/tcg/sparc/
H A Dtcg-target.c770 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
982 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
/external/qemu/tcg/hppa/
H A Dtcg-target.c939 tcg_out_andi(s, r0, addrlo, TARGET_PAGE_MASK | ((1 << s_bits) - 1));

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