Searched refs:TRI (Results 1 - 25 of 139) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp31 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
39 if (MF->getTarget().getRegisterInfo() != TRI) {
40 TRI = MF->getTarget().getRegisterInfo();
41 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
46 const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
51 CSRNum.resize(TRI->getNumRegs(), 0);
53 for (const uint16_t *AS = TRI->getOverlaps(Reg);
61 BitVector RR = TRI->getReservedRegs(*MF);
111 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
118 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
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H A DMachineRegisterInfo.cpp20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) argument
21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
24 UsedPhysRegs.resize(TRI.getNumRegs());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
226 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
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H A DRegisterScavenging.cpp40 for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
48 for (const uint16_t *R = TRI->getAliasSet(Reg); *R; ++R)
80 TRI = TM.getRegisterInfo();
83 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
93 NumPhysRegs = TRI->getNumRegs();
99 ReservedRegs = TRI->getReservedRegs(MF);
103 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
117 for (const uint16_t *R = TRI->getSubRegisters(Reg); *R; R++)
198 for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
216 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MR
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H A DMachineCopyPropagation.cpp34 const TargetRegisterInfo *TRI; member in class:__anon7364::MachineCopyPropagation
73 for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR)
78 for (const uint16_t *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
86 for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR)
123 const TargetRegisterInfo *TRI) {
127 if (TRI->isSubRegister(SrcSrc, Def)) {
129 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
132 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
163 isNopCopy(CopyMI, Def, Src, TRI)) {
181 I->clearRegisterKills(Def, TRI);
122 isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src, const TargetRegisterInfo *TRI) argument
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H A DRegisterCoalescer.h30 const TargetRegisterInfo &TRI; member in class:llvm::CoalescerPair
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
H A DAllocationOrder.cpp42 const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); local
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
60 Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
H A DVirtRegMap.cpp53 TRI = mf.getTarget().getRegisterInfo();
86 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
116 BitVector Reserved = TRI->getReservedRegs(*MF);
165 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
177 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
180 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
183 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
206 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
212 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo(); local
219 OS << '[' << PrintReg(Reg, TRI) << "
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H A DAggressiveAntiDepBreaker.cpp123 TRI(MF.getTarget().getRegisterInfo()),
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
139 dbgs() << " " << TRI->getName(r));
149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
160 for (const uint16_t *Alias = TRI->getOverlaps(*I);
176 for (const uint16_t *Alias = TRI->getOverlaps(*I);
189 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
192 for (const uint16_t *Alias = TRI->getOverlaps(Reg);
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
229 dbgs() << " " << TRI
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H A DLocalStackSlotAllocation.cpp86 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
91 if (!TRI->requiresVirtualBaseRegisters(MF) || LocalObjectCount == 0)
202 const TargetRegisterInfo *TRI) {
209 if (TRI->isFrameOffsetLegal(MI, Offset))
225 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local
289 if (TRI->needsFrameBaseReg(MI, LocalOffsets[FrameIdx])) {
306 MI, TRI)) {
316 int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx);
317 const TargetRegisterClass *RC = TRI->getPointerRegClass();
327 TRI
197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, std::pair<unsigned, int64_t> &RegOffset, int64_t FrameSizeAdjust, int64_t LocalFrameOffset, const MachineInstr *MI, const TargetRegisterInfo *TRI) argument
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H A DCriticalAntiDepBreaker.cpp34 TRI(MF.getTarget().getRegisterInfo()),
36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
37 KillIndices(TRI->getNumRegs(), 0),
38 DefIndices(TRI->getNumRegs(), 0),
39 KeepRegs(TRI->getNumRegs(), false) {}
46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
71 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
93 for (const uint16_t *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
106 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
114 for (const uint16_t *Alias = TRI
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H A DInterferenceCache.h24 const TargetRegisterInfo *TRI; member in class:llvm::InterferenceCache
97 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
102 const TargetRegisterInfo *TRI,
132 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
H A DRegAllocBase.cpp59 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
77 TRI->getName(PhysReg) << "\n";
101 TRI = &vrm.getTargetRegInfo();
108 const unsigned NumRegs = TRI->getNumRegs();
147 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
148 << " to " << PrintReg(PhysReg, TRI) << '\n');
157 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
158 << " from " << PrintReg(PhysReg, TRI) << '\n');
239 for (const uint16_t *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
257 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " liv
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/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.h41 const TargetRegisterInfo *TRI) const;
45 const TargetRegisterInfo *TRI) const;
H A DARMHazardRecognizer.h32 const ARMBaseRegisterInfo &TRI; member in class:llvm::ARMHazardRecognizer
45 TRI(tri), STI(sti), LastMI(0) {}
H A DThumb1InstrInfo.h50 const TargetRegisterInfo *TRI) const;
56 const TargetRegisterInfo *TRI) const;
H A DThumb2InstrInfo.h52 const TargetRegisterInfo *TRI) const;
58 const TargetRegisterInfo *TRI) const;
63 const TargetRegisterInfo &TRI) const;
H A DARMHazardRecognizer.cpp20 const TargetRegisterInfo &TRI) {
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
61 hasRAWHazard(DefMI, MI, TRI))) {
19 hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h37 const TargetRegisterInfo *TRI) const;
42 const TargetRegisterInfo *TRI) const;
H A DHexagonFrameLowering.cpp217 const TargetRegisterInfo *TRI) const {
238 const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
246 const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
249 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);
256 CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
262 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
264 TRI);
276 const TargetRegisterInfo *TRI) const {
298 const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
305 const uint16_t* SuperRegNext = TRI
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/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.h41 const TargetRegisterInfo *TRI) const;
45 const TargetRegisterInfo *TRI) const;
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.h37 const TargetRegisterInfo *TRI) const;
41 const TargetRegisterInfo *TRI) const;
/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp37 else if (TRI && Reg < TRI->getNumRegs())
38 OS << '%' << TRI->getName(Reg);
42 if (TRI)
43 OS << ':' << TRI->getSubRegIndexName(SubIdx);
H A DTargetInstrInfo.cpp31 const TargetRegisterInfo *TRI) const {
37 return TRI->getPointerRegClass(RegClass);
44 return TRI->getRegClass(RegClass);
/external/llvm/include/llvm/CodeGen/
H A DMachineInstr.h646 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
647 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
667 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
668 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
675 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
676 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
682 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
683 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
690 const TargetRegisterInfo *TRI = NULL) const {
691 return findRegisterDefOperandIdx(Reg, true, false, TRI) !
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H A DProcessImplicitDefs.h29 const TargetRegisterInfo *TRI; member in class:llvm::ProcessImplicitDefs

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