Searched refs:active_fpu (Results 1 - 7 of 7) sorted by relevance

/external/qemu/target-mips/
H A Dop_helper.c1961 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1964 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
1972 arg1 = (int32_t)env->active_fpu.fcr0;
1975 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1978 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
1981 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu
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H A Dexec.h80 if (env->active_fpu.fcr0 & (1 << FCR0_F64))
H A Dmachine.c52 save_fpu(f, &env->active_fpu);
203 load_fpu(f, &env->active_fpu);
H A Dtranslate_init.c526 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
H A Dcpu.h176 CPUMIPSFPUContext active_fpu; member in struct:CPUMIPSState
H A Dtranslate.c597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
633 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
8454 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
8455 get_float_exception_flags(&env->active_fpu
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/external/qemu/
H A Dgdbstub.c988 GET_REGL(env->active_fpu.fpr[n - 38].d);
990 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
993 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
994 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1024 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1040 env->active_fpu.fpr[n - 38].d = tmp;
1042 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1046 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1051 SET_FP_ENABLE(env->active_fpu
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