1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This file is subject to the terms and conditions of the GNU General Public 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * License. See the file "COPYING" in the main directory of this archive 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * for more details. 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ioc.h: Definitions for SGI I/O Controller 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1996 David S. Miller 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2001, 2003 Ladislav Michl 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _SGI_IOC_H 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define _SGI_IOC_H 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <linux/types.h> 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/sgi/pi1.h> 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * All registers are 8-bit wide alligned on 32-bit boundary. Bad things 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * happen if you try word access them. You have been warned. 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct sgioc_uart_regs { 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _ctrl1[3]; 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 ctrl1; 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _data1[3]; 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 data1; 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _ctrl2[3]; 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 ctrl2; 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _data2[3]; 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 data2; 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct sgioc_keyb_regs { 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _data[3]; 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 data; 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _command[3]; 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 command; 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct sgint_regs { 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _istat0[3]; 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 istat0; /* Interrupt status zero */ 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_FFULL 0x01 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_SCSI0 0x02 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_SCSI1 0x04 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_ENET 0x08 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_GFXDMA 0x10 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_PPORT 0x20 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_HPC2 0x40 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT0_LIO2 0x80 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _imask0[3]; 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 imask0; /* Interrupt mask zero */ 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _istat1[3]; 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 istat1; /* Interrupt status one */ 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_ISDNI 0x01 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_PWR 0x02 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_ISDNH 0x04 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_LIO3 0x08 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_HPC3 0x10 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_AFAIL 0x20 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_VIDEO 0x40 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_ISTAT1_GIO2 0x80 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _imask1[3]; 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 imask1; /* Interrupt mask one */ 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _vmeistat[3]; 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 vmeistat; /* VME interrupt status */ 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _cmeimask0[3]; 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 cmeimask0; /* VME interrupt mask zero */ 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _cmeimask1[3]; 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 cmeimask1; /* VME interrupt mask one */ 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _cmepol[3]; 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 cmepol; /* VME polarity */ 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _tclear[3]; 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 tclear; 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _errstat[3]; 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 errstat; /* Error status reg, reserved on INT2 */ 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused0[2]; 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _tcnt0[3]; 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 tcnt0; /* counter 0 */ 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _tcnt1[3]; 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 tcnt1; /* counter 1 */ 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _tcnt2[3]; 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 tcnt2; /* counter 2 */ 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _tcword[3]; 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 tcword; /* control word */ 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CMASK 0x30 /* Command mask */ 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CLAT 0x00 /* Latch command */ 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ 105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz 109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TIMER_CLOCK 1000000 111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This is the constant we're using for calibrating the counter. 114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255) 116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* We need software copies of these because they are write only. */ 118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern u8 sgi_ioc_reset, sgi_ioc_write; 119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct sgioc_regs { 121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct pi1_regs pport; 122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused0[2]; 123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct sgioc_uart_regs uart; 124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct sgioc_keyb_regs kbdmouse; 125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _gcsel[3]; 126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 gcsel; 127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _genctrl[3]; 128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 genctrl; 129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _panel[3]; 130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 panel; 131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_PANEL_POWERON 0x01 132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_PANEL_POWERINTR 0x02 133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_PANEL_VOLDNINTR 0x10 134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_PANEL_VOLDNHOLD 0x20 135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_PANEL_VOLUPINTR 0x40 136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_PANEL_VOLUPHOLD 0x80 137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused1; 138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _sysid[3]; 139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 sysid; 140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_SYSID_FULLHOUSE 0x01 141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1) 142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5) 143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused2; 144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _read[3]; 145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 read; 146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused3; 147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _dmasel[3]; 148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 dmasel; 149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ 150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ 151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ 152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ 153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ 154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */ 155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused4; 156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _reset[3]; 157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 reset; 158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */ 159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */ 160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */ 161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */ 162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */ 163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */ 164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused5; 165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 _write[3]; 166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 write; 167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ 168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ 169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ 170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ 171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ 172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ 173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */ 174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */ 175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused6; 176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct sgint_regs int3; 177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 _unused7[16]; 178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 extio; /* FullHouse only */ 179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */ 180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */ 181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */ 182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_S0_RETRACE 0x1000 183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */ 184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */ 185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */ 186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_SG_RETRACE 0x0100 187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_GIO_33MHZ 0x0080 188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_EISA_BUSERR 0x0040 189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_MC_BUSERR 0x0020 190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_HPC3_BUSERR 0x0010 191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_S0_STAT_1 0x0008 192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_S0_STAT_0 0x0004 193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_SG_STAT_1 0x0002 194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXTIO_SG_STAT_0 0x0001 195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern struct sgioc_regs *sgioc; 198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern struct sgint_regs *sgint; 199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 201