TargetInstrInfoImpl.cpp revision 1e2ec6abd4e150ac87d6cde3133fa9895f63c74c
1641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===// 2641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 3641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// The LLVM Compiler Infrastructure 4641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 5641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file is distributed under the University of Illinois Open Source 6641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// License. See LICENSE.TXT for details. 7641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 8641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 9641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 10641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file implements the TargetInstrInfoImpl class, it just provides default 11641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// implementations of various methods. 12641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 13641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 14641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 15641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/Target/TargetInstrInfo.h" 1686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng#include "llvm/Target/TargetLowering.h" 17a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetMachine.h" 18a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson#include "llvm/ADT/SmallVector.h" 20c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/MachineFrameInfo.h" 21641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/CodeGen/MachineInstr.h" 2258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 23c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman#include "llvm/CodeGen/MachineMemOperand.h" 24a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 256b1207267f01877ff9b351786c902cb2ecd354c0Andrew Trick#include "llvm/CodeGen/ScoreboardHazardRecognizer.h" 26c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/PseudoSourceValue.h" 27028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky#include "llvm/MC/MCInstrItineraries.h" 28c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick#include "llvm/Support/CommandLine.h" 299fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen#include "llvm/Support/Debug.h" 3034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/ErrorHandling.h" 3134c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/raw_ostream.h" 32641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerusing namespace llvm; 33641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 34c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trickstatic cl::opt<bool> DisableHazardRecognizer( 35c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick "disable-sched-hazard", cl::Hidden, cl::init(false), 36c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick cl::desc("Disable hazard detection during preRA scheduling")); 37c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 384d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 394d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// after it, replacing it with an unconditional branch to NewDest. 4086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengvoid 4186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan ChengTargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 4286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const { 4386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *MBB = Tail->getParent(); 4486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the old successors of MBB from the CFG. 4686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng while (!MBB->succ_empty()) 4786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->removeSuccessor(MBB->succ_begin()); 4886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the dead instructions from the end of MBB. 5086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->erase(Tail, MBB->end()); 5186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 5286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // If MBB isn't immediately before MBB, insert a branch to it. 5386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) 5486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(), 5586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng Tail->getDebugLoc()); 5686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->addSuccessor(NewDest); 5786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 5886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 59641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// commuteInstruction - The default implementation of this method just exchanges 6034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng// the two operands returned by findCommutedOpIndices. 6158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, 6258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI) const { 63e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 64e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool HasDef = MCID.getNumDefs(); 6534c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (HasDef && !MI->getOperand(0).isReg()) 6634c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng // No idea how to commute this instruction. Target should implement its own. 6734c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng return 0; 6834c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng unsigned Idx1, Idx2; 6934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (!findCommutedOpIndices(MI, Idx1, Idx2)) { 7034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng std::string msg; 7134c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng raw_string_ostream Msg(msg); 7234c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng Msg << "Don't know how to commute: " << *MI; 7375361b69f3f327842b9dad69fa7f28ae3b688412Chris Lattner report_fatal_error(Msg.str()); 7434c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng } 75498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng 76498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && 77641055225092833197efe8e5bce01d50bcf1daaeChris Lattner "This only knows how to commute register operands so far"); 78cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; 79498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg1 = MI->getOperand(Idx1).getReg(); 80498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg2 = MI->getOperand(Idx2).getReg(); 81498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg1IsKill = MI->getOperand(Idx1).isKill(); 82498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg2IsKill = MI->getOperand(Idx2).isKill(); 83cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng // If destination is tied to either of the commuted source register, then 84cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng // it must be updated. 85cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng if (HasDef && Reg0 == Reg1 && 86cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { 87a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 88cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng Reg0 = Reg2; 89cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng } else if (HasDef && Reg0 == Reg2 && 90cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { 91cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng Reg1IsKill = false; 92cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng Reg0 = Reg1; 9358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 9458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 9558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 9658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 97498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; 988e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 99498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef) 100498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 101498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 102498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 103498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 104498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng else 105498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 106498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 107498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 108a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 10958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 110cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng if (HasDef) 111cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71Evan Cheng MI->getOperand(0).setReg(Reg0); 112498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setReg(Reg1); 113498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setReg(Reg2); 114498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setIsKill(Reg1IsKill); 115498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setIsKill(Reg2IsKill); 116641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MI; 117641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 118641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 119261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// findCommutedOpIndices - If specified MI is commutable, return the two 120261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// operand indices that would swap value. Return true if the instruction 121261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// is not in a form which this routine understands. 122261ce1d5f89155d2e6f914f281db2004c89ee839Evan Chengbool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI, 123261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx1, 124261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const { 125ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!MI->isBundle() && 1265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng "TargetInstrInfoImpl::findCommutedOpIndices() can't handle bundles"); 1275a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 128e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 129e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (!MCID.isCommutable()) 130498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return false; 131261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this 132261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // is not true, then the target must implement this. 133e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng SrcOpIdx1 = MCID.getNumDefs(); 134261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx2 = SrcOpIdx1 + 1; 135261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!MI->getOperand(SrcOpIdx1).isReg() || 136261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng !MI->getOperand(SrcOpIdx2).isReg()) 137261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // No idea. 138261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return false; 139261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return true; 140f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng} 141f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 142f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 14332f9763017f4329a0da75648655d63c9d7b91130Evan Chengbool 14432f9763017f4329a0da75648655d63c9d7b91130Evan ChengTargetInstrInfoImpl::isUnpredicatedTerminator(const MachineInstr *MI) const { 14532f9763017f4329a0da75648655d63c9d7b91130Evan Cheng if (!MI->isTerminator()) return false; 14632f9763017f4329a0da75648655d63c9d7b91130Evan Cheng 14732f9763017f4329a0da75648655d63c9d7b91130Evan Cheng // Conditional branch is a special case. 14832f9763017f4329a0da75648655d63c9d7b91130Evan Cheng if (MI->isBranch() && !MI->isBarrier()) 14932f9763017f4329a0da75648655d63c9d7b91130Evan Cheng return true; 15032f9763017f4329a0da75648655d63c9d7b91130Evan Cheng if (!MI->isPredicable()) 15132f9763017f4329a0da75648655d63c9d7b91130Evan Cheng return true; 15232f9763017f4329a0da75648655d63c9d7b91130Evan Cheng return !isPredicated(MI); 15332f9763017f4329a0da75648655d63c9d7b91130Evan Cheng} 15432f9763017f4329a0da75648655d63c9d7b91130Evan Cheng 15532f9763017f4329a0da75648655d63c9d7b91130Evan Cheng 156641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerbool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, 15744eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const { 158641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool MadeChange = false; 1595a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 160ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng assert(!MI->isBundle() && 1615a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng "TargetInstrInfoImpl::PredicateInstruction() can't handle bundles"); 1625a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 163e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = MI->getDesc(); 1645a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (!MI->isPredicable()) 165749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return false; 1666b1207267f01877ff9b351786c902cb2ecd354c0Andrew Trick 167749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { 168e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (MCID.OpInfo[i].isPredicate()) { 169749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MachineOperand &MO = MI->getOperand(i); 170d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) { 171749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setReg(Pred[j].getReg()); 172749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 173d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isImm()) { 174749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setImm(Pred[j].getImm()); 175749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 176d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isMBB()) { 177749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setMBB(Pred[j].getMBB()); 178749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 179641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 180749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner ++j; 181641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 182641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 183641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MadeChange; 184641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 185ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 1862df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesenbool TargetInstrInfoImpl::hasLoadFromStackSlot(const MachineInstr *MI, 1872df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen const MachineMemOperand *&MMO, 1882df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen int &FrameIndex) const { 1892df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 1902df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen oe = MI->memoperands_end(); 1912df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen o != oe; 1922df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen ++o) { 1932df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen if ((*o)->isLoad() && (*o)->getValue()) 1942df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen if (const FixedStackPseudoSourceValue *Value = 1952df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 1962df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen FrameIndex = Value->getFrameIndex(); 1972df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen MMO = *o; 1982df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen return true; 1992df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen } 2002df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen } 2012df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen return false; 2022df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen} 2032df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen 2042df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesenbool TargetInstrInfoImpl::hasStoreToStackSlot(const MachineInstr *MI, 2052df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen const MachineMemOperand *&MMO, 2062df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen int &FrameIndex) const { 2072df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 2082df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen oe = MI->memoperands_end(); 2092df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen o != oe; 2102df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen ++o) { 2112df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen if ((*o)->isStore() && (*o)->getValue()) 2122df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen if (const FixedStackPseudoSourceValue *Value = 2132df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 2142df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen FrameIndex = Value->getFrameIndex(); 2152df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen MMO = *o; 2162df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen return true; 2172df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen } 2182df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen } 2192df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen return false; 2202df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen} 2212df3f58a0b3937f2cbd76d3417d2905ca86cf8faJakob Stoklund Olesen 222ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Chengvoid TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, 223ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator I, 224ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 225378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned SubIdx, 226d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 2279edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 2288e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 2299edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 230ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MBB.insert(I, MI); 231ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng} 232ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 2339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool 2349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan ChengTargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0, 2359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 2369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 237506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 238506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng} 239506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng 24030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig, 24130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const { 2425a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng assert(!Orig->isNotDuplicable() && 24330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Instruction cannot be duplicated"); 24430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MF.CloneMachineInstr(Orig); 24530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 24630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 2471f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen// If the COPY instruction in MI can be folded to a stack operation, return 2481f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen// the register class to use. 2491f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesenstatic const TargetRegisterClass *canFoldCopy(const MachineInstr *MI, 2501f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned FoldIdx) { 2511f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(MI->isCopy() && "MI must be a COPY instruction"); 2521f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (MI->getNumOperands() != 2) 2531f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 2541f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand"); 2551f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2561f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineOperand &FoldOp = MI->getOperand(FoldIdx); 2571f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx); 2581f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2591f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (FoldOp.getSubReg() || LiveOp.getSubReg()) 2601f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 2611f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2621f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned FoldReg = FoldOp.getReg(); 2631f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned LiveReg = LiveOp.getReg(); 2641f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2651f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(TargetRegisterInfo::isVirtualRegister(FoldReg) && 2661f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen "Cannot fold physregs"); 2671f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2681f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 2691f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 2701f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2711f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg())) 2721f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return RC->contains(LiveOp.getReg()) ? RC : 0; 2731f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 274fa226bccaa90c520cac154df74069bbabb976eabJakob Stoklund Olesen if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 2751f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return RC; 2761f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2771f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen // FIXME: Allow folding when register classes are memory compatible. 2781f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 2791f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen} 2801f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2811f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesenbool TargetInstrInfoImpl:: 2821f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund OlesencanFoldMemoryOperand(const MachineInstr *MI, 2831f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const SmallVectorImpl<unsigned> &Ops) const { 2841f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]); 2851f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen} 2861f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 287c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Attempt to fold a load or store of the specified stack 288c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// slot into the specified machine instruction for the specified operand(s). 289c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// If this is possible, a new instruction is returned with the specified 290c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// operand folded, otherwise NULL is returned. The client is responsible for 291c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// removing the old instruction and adding the new one in the instruction 292c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stream. 293c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 294e05442d50806e2850eae1571958816028093df85Jakob Stoklund OlesenTargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, 295c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 2961f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen int FI) const { 297c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman unsigned Flags = 0; 298c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 299c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (MI->getOperand(Ops[i]).isDef()) 300c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOStore; 301c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman else 302c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOLoad; 303c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 3041f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen MachineBasicBlock *MBB = MI->getParent(); 3051f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(MBB && "foldMemoryOperand needs an inserted instruction"); 3061f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen MachineFunction &MF = *MBB->getParent(); 307e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen 308c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 3099fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) { 3109fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // Add a memory operand, foldMemoryOperandImpl doesn't do that. 3119fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert((!(Flags & MachineMemOperand::MOStore) || 3125a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng NewMI->mayStore()) && 3139fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen "Folded a def to a non-store!"); 3149fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert((!(Flags & MachineMemOperand::MOLoad) || 3155a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng NewMI->mayLoad()) && 3169fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen "Folded a use to a non-load!"); 3179fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 3189fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert(MFI.getObjectOffset(FI) != -1); 3199fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MachineMemOperand *MMO = 320f4a5084d06438fcd7f91684b6236b66c4c202e16Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 32193a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner Flags, MFI.getObjectSize(FI), 3229fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MFI.getObjectAlignment(FI)); 3239fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->addMemOperand(MF, MMO); 3241f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 3259fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI. 3269fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return MBB->insert(MI, NewMI); 3279fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen } 3281f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 3299fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // Straight COPY may fold as load/store. 3309fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (!MI->isCopy() || Ops.size() != 1) 3319fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return 0; 3321f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 3339fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); 3349fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (!RC) 3359fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return 0; 3361f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 3379fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(1-Ops[0]); 3389fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MachineBasicBlock::iterator Pos = MI; 3399fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 3401f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 3419fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (Flags == MachineMemOperand::MOStore) 3429fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 3439fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen else 3449fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); 3459fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return --Pos; 346c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 347c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 348c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Same as the previous version except it allows folding 349c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// of any load and store from / to any address, not just from a specific 350c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stack slot. 351c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 352e05442d50806e2850eae1571958816028093df85Jakob Stoklund OlesenTargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, 353c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 354c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 3555a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!"); 356c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#ifndef NDEBUG 357c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 358c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); 359c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#endif 360e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineBasicBlock &MBB = *MI->getParent(); 361e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineFunction &MF = *MBB.getParent(); 362c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 363c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 364c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI); 365c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (!NewMI) return 0; 366c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 367e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen NewMI = MBB.insert(MI, NewMI); 368e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen 369c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Copy the memoperands from the load to the folded instruction. 370c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman NewMI->setMemRefs(LoadMI->memoperands_begin(), 371c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman LoadMI->memoperands_end()); 372c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 373c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return NewMI; 374c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 375a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 37644acc24117b1a9eafb7b9b993731ca0115569ea2Evan Chengbool TargetInstrInfo:: 37744acc24117b1a9eafb7b9b993731ca0115569ea2Evan ChengisReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 37844acc24117b1a9eafb7b9b993731ca0115569ea2Evan Cheng AliasAnalysis *AA) const { 379a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineFunction &MF = *MI->getParent()->getParent(); 380a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineRegisterInfo &MRI = MF.getRegInfo(); 381a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetMachine &TM = MF.getTarget(); 382a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrInfo &TII = *TM.getInstrInfo(); 383a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 384a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 3854a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen // Remat clients assume operand 0 is the defined register. 3864a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) 3874a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen return false; 3884a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen unsigned DefReg = MI->getOperand(0).getReg(); 3894a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen 3909d548d0343774636e72713d678a078c8e808ed29Jakob Stoklund Olesen // A sub-register definition can only be rematerialized if the instruction 3919d548d0343774636e72713d678a078c8e808ed29Jakob Stoklund Olesen // doesn't read the other parts of the register. Otherwise it is really a 3929d548d0343774636e72713d678a078c8e808ed29Jakob Stoklund Olesen // read-modify-write operation on the full virtual register which cannot be 3939d548d0343774636e72713d678a078c8e808ed29Jakob Stoklund Olesen // moved safely. 3944a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(DefReg) && 3954a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) 3969d548d0343774636e72713d678a078c8e808ed29Jakob Stoklund Olesen return false; 3979d548d0343774636e72713d678a078c8e808ed29Jakob Stoklund Olesen 398a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A load from a fixed stack slot can be rematerialized. This may be 399a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // redundant with subsequent checks, but it's target-independent, 400a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // simple, and a common case. 401a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman int FrameIdx = 0; 402a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TII.isLoadFromStackSlot(MI, FrameIdx) && 403a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx)) 404a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 405a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 406a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions obviously unsafe for remat. 4075a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isNotDuplicable() || MI->mayStore() || 408c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng MI->hasUnmodeledSideEffects()) 409c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng return false; 410c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng 411c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // Don't remat inline asm. We have no idea how expensive it is 412c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // even if it's side effect free. 413c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng if (MI->isInlineAsm()) 414a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 415a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 416a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions which load from potentially varying memory. 4175a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->mayLoad() && !MI->isInvariantLoad(AA)) 418a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 419a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 420a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If any of the registers accessed are non-constant, conservatively assume 421a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // the instruction is not rematerializable. 422a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 423a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineOperand &MO = MI->getOperand(i); 424a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MO.isReg()) continue; 425a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned Reg = MO.getReg(); 426a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (Reg == 0) 427a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 428a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 429a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a well-behaved physical register. 430a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 431a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) { 432a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If the physreg has no defs anywhere, it's just an ambient register 433a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // and we can freely move its uses. Alternatively, if it's allocatable, 434a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // it could get allocated to something with a def during allocation. 435a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(Reg)) 436a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 437a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0); 438a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(Reg)) 439a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 440a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a def among the register's aliases too. 441a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) { 442a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned AliasReg = *Alias; 443a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(AliasReg)) 444a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 445a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(AliasReg)) 446a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 447a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 448a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } else { 449a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A physreg def. We can't remat it. 450a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 451a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 452a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 453a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 454a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 4554a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen // Only allow one virtual-register def. There may be multiple defs of the 4564a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen // same virtual register, though. 4574a0a18af4a9a47466a6077a158387ba4f57bf636Jakob Stoklund Olesen if (MO.isDef() && Reg != DefReg) 458a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 459a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 460a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Don't allow any virtual-register uses. Rematting an instruction with 461a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // virtual register uses would length the live ranges of the uses, which 462a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // is not necessarily a good idea, certainly not "trivial". 463a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) 464a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 465a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 466a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 467a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Everything checked out. 468a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 469a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman} 470774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng 47186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// isSchedulingBoundary - Test if the given instruction should be 47286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// considered a scheduling boundary. This primarily includes labels 47386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// and terminators. 47486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI, 47586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 47686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const{ 47786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 4785a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isTerminator() || MI->isLabel()) 47986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 48086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 48186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 48286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 48386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 48486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 48586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 48686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); 48786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore())) 48886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 48986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 49086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 49186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 49286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 493c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick// Provide a global flag for disabling the PreRA hazard recognizer that targets 494c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick// may choose to honor. 495c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trickbool TargetInstrInfoImpl::usePreRAHazardRecognizer() const { 496c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return !DisableHazardRecognizer; 497c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick} 498c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 499c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick// Default implementation of CreateTargetRAHazardRecognizer. 5002da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *TargetInstrInfoImpl:: 5012da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 5022da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 5032da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick // Dummy hazard recognizer allows all instructions to issue. 5042da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScheduleHazardRecognizer(); 5052da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 5062da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 507774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng// Default implementation of CreateTargetPostRAHazardRecognizer. 508774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan ChengScheduleHazardRecognizer *TargetInstrInfoImpl:: 5092da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 5102da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 5112da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return (ScheduleHazardRecognizer *) 5122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched"); 513774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng} 514028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 515028700f544deeea423ce9b516e190e4e970e3c6cNick Lewyckyint 5161e2ec6abd4e150ac87d6cde3133fa9895f63c74cEli FriedmanTargetInstrInfoImpl::getOperandLatency(const InstrItineraryData *ItinData, 5171e2ec6abd4e150ac87d6cde3133fa9895f63c74cEli Friedman SDNode *DefNode, unsigned DefIdx, 5181e2ec6abd4e150ac87d6cde3133fa9895f63c74cEli Friedman SDNode *UseNode, unsigned UseIdx) const { 519028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky if (!ItinData || ItinData->isEmpty()) 520028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return -1; 521028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 522028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky if (!DefNode->isMachineOpcode()) 523028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return -1; 524028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 525028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); 526028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky if (!UseNode->isMachineOpcode()) 527028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return ItinData->getOperandCycle(DefClass, DefIdx); 528028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); 529028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 530028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky} 531028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 5321e2ec6abd4e150ac87d6cde3133fa9895f63c74cEli Friedmanint TargetInstrInfoImpl::getInstrLatency(const InstrItineraryData *ItinData, 5331e2ec6abd4e150ac87d6cde3133fa9895f63c74cEli Friedman SDNode *N) const { 534028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky if (!ItinData || ItinData->isEmpty()) 535028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return 1; 536028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 537028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky if (!N->isMachineOpcode()) 538028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return 1; 539028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 540028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); 541028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky} 542028700f544deeea423ce9b516e190e4e970e3c6cNick Lewycky 543