TargetInstrInfoImpl.cpp revision fa226bccaa90c520cac154df74069bbabb976eab
1641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===// 2641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 3641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// The LLVM Compiler Infrastructure 4641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 5641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file is distributed under the University of Illinois Open Source 6641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// License. See LICENSE.TXT for details. 7641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 8641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 9641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 10641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// This file implements the TargetInstrInfoImpl class, it just provides default 11641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// implementations of various methods. 12641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// 13641055225092833197efe8e5bce01d50bcf1daaeChris Lattner//===----------------------------------------------------------------------===// 14641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 15641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/Target/TargetInstrInfo.h" 1686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng#include "llvm/Target/TargetLowering.h" 17a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetMachine.h" 18a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson#include "llvm/ADT/SmallVector.h" 20c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/MachineFrameInfo.h" 21641055225092833197efe8e5bce01d50bcf1daaeChris Lattner#include "llvm/CodeGen/MachineInstr.h" 2258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 23c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman#include "llvm/CodeGen/MachineMemOperand.h" 24a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 256b1207267f01877ff9b351786c902cb2ecd354c0Andrew Trick#include "llvm/CodeGen/ScoreboardHazardRecognizer.h" 26c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#include "llvm/CodeGen/PseudoSourceValue.h" 27c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick#include "llvm/Support/CommandLine.h" 289fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen#include "llvm/Support/Debug.h" 2934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/ErrorHandling.h" 3034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng#include "llvm/Support/raw_ostream.h" 31641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerusing namespace llvm; 32641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 33c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trickstatic cl::opt<bool> DisableHazardRecognizer( 34c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick "disable-sched-hazard", cl::Hidden, cl::init(false), 35c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick cl::desc("Disable hazard detection during preRA scheduling")); 36c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 374d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 384d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng/// after it, replacing it with an unconditional branch to NewDest. 3986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengvoid 4086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan ChengTargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 4186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const { 4286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *MBB = Tail->getParent(); 4386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the old successors of MBB from the CFG. 4586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng while (!MBB->succ_empty()) 4686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->removeSuccessor(MBB->succ_begin()); 4786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 4886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Remove all the dead instructions from the end of MBB. 4986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->erase(Tail, MBB->end()); 5086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 5186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // If MBB isn't immediately before MBB, insert a branch to it. 5286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) 5386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(), 5486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng Tail->getDebugLoc()); 5586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MBB->addSuccessor(NewDest); 5686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 5786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 58641055225092833197efe8e5bce01d50bcf1daaeChris Lattner// commuteInstruction - The default implementation of this method just exchanges 5934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng// the two operands returned by findCommutedOpIndices. 6058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, 6158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI) const { 62498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng const TargetInstrDesc &TID = MI->getDesc(); 63498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool HasDef = TID.getNumDefs(); 6434c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (HasDef && !MI->getOperand(0).isReg()) 6534c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng // No idea how to commute this instruction. Target should implement its own. 6634c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng return 0; 6734c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng unsigned Idx1, Idx2; 6834c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng if (!findCommutedOpIndices(MI, Idx1, Idx2)) { 6934c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng std::string msg; 7034c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng raw_string_ostream Msg(msg); 7134c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng Msg << "Don't know how to commute: " << *MI; 7275361b69f3f327842b9dad69fa7f28ae3b688412Chris Lattner report_fatal_error(Msg.str()); 7334c75093f085c7958fa3bd31f3c4a50942d83505Evan Cheng } 74498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng 75498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && 76641055225092833197efe8e5bce01d50bcf1daaeChris Lattner "This only knows how to commute register operands so far"); 77498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg1 = MI->getOperand(Idx1).getReg(); 78498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg2 = MI->getOperand(Idx2).getReg(); 79498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg1IsKill = MI->getOperand(Idx1).isKill(); 80498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg2IsKill = MI->getOperand(Idx2).isKill(); 8158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 82498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef && MI->getOperand(0).getReg() == Reg1) { 83a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 84a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 85a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 86a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 8758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 8858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 8958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 9058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 9158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 92498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng unsigned Reg0 = HasDef 93498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; 94498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; 958e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 96498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng if (HasDef) 97498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 98498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 99498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 100498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 101498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng else 102498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 103498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg2, getKillRegState(Reg2IsKill)) 104498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng .addReg(Reg1, getKillRegState(Reg2IsKill)); 105a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 10658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 10758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 10858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 109498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setReg(Reg1); 110498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setReg(Reg2); 111498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx2).setIsKill(Reg1IsKill); 112498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng MI->getOperand(Idx1).setIsKill(Reg2IsKill); 113641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MI; 114641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 115641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 116261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// findCommutedOpIndices - If specified MI is commutable, return the two 117261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// operand indices that would swap value. Return true if the instruction 118261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng/// is not in a form which this routine understands. 119261ce1d5f89155d2e6f914f281db2004c89ee839Evan Chengbool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI, 120261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx1, 121261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const { 122498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng const TargetInstrDesc &TID = MI->getDesc(); 123261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!TID.isCommutable()) 124498c2903e28b56b73b8056335ad7f1eb6347b8edEvan Cheng return false; 125261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this 126261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // is not true, then the target must implement this. 127261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx1 = TID.getNumDefs(); 128261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng SrcOpIdx2 = SrcOpIdx1 + 1; 129261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng if (!MI->getOperand(SrcOpIdx1).isReg() || 130261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng !MI->getOperand(SrcOpIdx2).isReg()) 131261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng // No idea. 132261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return false; 133261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng return true; 134f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng} 135f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 136f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 137641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerbool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, 13844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const { 139641055225092833197efe8e5bce01d50bcf1daaeChris Lattner bool MadeChange = false; 140749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &TID = MI->getDesc(); 141749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (!TID.isPredicable()) 142749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return false; 1436b1207267f01877ff9b351786c902cb2ecd354c0Andrew Trick 144749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { 145749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner if (TID.OpInfo[i].isPredicate()) { 146749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MachineOperand &MO = MI->getOperand(i); 147d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) { 148749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setReg(Pred[j].getReg()); 149749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 150d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isImm()) { 151749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setImm(Pred[j].getImm()); 152749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 153d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman } else if (MO.isMBB()) { 154749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MO.setMBB(Pred[j].getMBB()); 155749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner MadeChange = true; 156641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 157749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner ++j; 158641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 159641055225092833197efe8e5bce01d50bcf1daaeChris Lattner } 160641055225092833197efe8e5bce01d50bcf1daaeChris Lattner return MadeChange; 161641055225092833197efe8e5bce01d50bcf1daaeChris Lattner} 162ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 163ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Chengvoid TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, 164ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator I, 165ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 166378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned SubIdx, 167d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1689edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const { 1698e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1709edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 171ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MBB.insert(I, MI); 172ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng} 173ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 1749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool 1759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan ChengTargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0, 1769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 1779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const { 178506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 179506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng} 180506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng 18130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund OlesenMachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig, 18230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const { 18330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen assert(!Orig->getDesc().isNotDuplicable() && 18430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen "Instruction cannot be duplicated"); 18530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen return MF.CloneMachineInstr(Orig); 18630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen} 18730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 1881f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen// If the COPY instruction in MI can be folded to a stack operation, return 1891f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen// the register class to use. 1901f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesenstatic const TargetRegisterClass *canFoldCopy(const MachineInstr *MI, 1911f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned FoldIdx) { 1921f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(MI->isCopy() && "MI must be a COPY instruction"); 1931f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (MI->getNumOperands() != 2) 1941f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 1951f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand"); 1961f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 1971f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineOperand &FoldOp = MI->getOperand(FoldIdx); 1981f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx); 1991f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2001f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (FoldOp.getSubReg() || LiveOp.getSubReg()) 2011f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 2021f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2031f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned FoldReg = FoldOp.getReg(); 2041f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen unsigned LiveReg = LiveOp.getReg(); 2051f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2061f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(TargetRegisterInfo::isVirtualRegister(FoldReg) && 2071f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen "Cannot fold physregs"); 2081f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2091f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 2101f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 2111f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2121f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg())) 2131f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return RC->contains(LiveOp.getReg()) ? RC : 0; 2141f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 215fa226bccaa90c520cac154df74069bbabb976eabJakob Stoklund Olesen if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 2161f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return RC; 2171f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2181f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen // FIXME: Allow folding when register classes are memory compatible. 2191f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return 0; 2201f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen} 2211f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2221f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesenbool TargetInstrInfoImpl:: 2231f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund OlesencanFoldMemoryOperand(const MachineInstr *MI, 2241f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const SmallVectorImpl<unsigned> &Ops) const { 2251f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]); 2261f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen} 2271f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 228c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Attempt to fold a load or store of the specified stack 229c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// slot into the specified machine instruction for the specified operand(s). 230c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// If this is possible, a new instruction is returned with the specified 231c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// operand folded, otherwise NULL is returned. The client is responsible for 232c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// removing the old instruction and adding the new one in the instruction 233c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stream. 234c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 235e05442d50806e2850eae1571958816028093df85Jakob Stoklund OlesenTargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, 236c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 2371f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen int FI) const { 238c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman unsigned Flags = 0; 239c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 240c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (MI->getOperand(Ops[i]).isDef()) 241c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOStore; 242c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman else 243c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman Flags |= MachineMemOperand::MOLoad; 244c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 2451f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen MachineBasicBlock *MBB = MI->getParent(); 2461f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen assert(MBB && "foldMemoryOperand needs an inserted instruction"); 2471f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen MachineFunction &MF = *MBB->getParent(); 248e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen 249c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 2509fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) { 2519fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // Add a memory operand, foldMemoryOperandImpl doesn't do that. 2529fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert((!(Flags & MachineMemOperand::MOStore) || 2539fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->getDesc().mayStore()) && 2549fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen "Folded a def to a non-store!"); 2559fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert((!(Flags & MachineMemOperand::MOLoad) || 2569fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->getDesc().mayLoad()) && 2579fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen "Folded a use to a non-load!"); 2589fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 2599fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen assert(MFI.getObjectOffset(FI) != -1); 2609fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MachineMemOperand *MMO = 26193a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner MF.getMachineMemOperand( 26293a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 26393a95ae8a9d8eb19dc0d90281473be2fb1c05a17Chris Lattner Flags, MFI.getObjectSize(FI), 2649fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MFI.getObjectAlignment(FI)); 2659fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen NewMI->addMemOperand(MF, MMO); 2661f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2679fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI. 2689fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return MBB->insert(MI, NewMI); 2699fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen } 2701f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2719fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen // Straight COPY may fold as load/store. 2729fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (!MI->isCopy() || Ops.size() != 1) 2739fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return 0; 2741f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2759fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); 2769fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (!RC) 2779fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return 0; 2781f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2799fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const MachineOperand &MO = MI->getOperand(1-Ops[0]); 2809fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen MachineBasicBlock::iterator Pos = MI; 2819fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 2821f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen 2839fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen if (Flags == MachineMemOperand::MOStore) 2849fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 2859fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen else 2869fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); 2879fac4159ddf65d90ebcccd80a0ba513cd8e95be1Jakob Stoklund Olesen return --Pos; 288c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 289c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 290c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// foldMemoryOperand - Same as the previous version except it allows folding 291c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// of any load and store from / to any address, not just from a specific 292c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman/// stack slot. 293c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr* 294e05442d50806e2850eae1571958816028093df85Jakob Stoklund OlesenTargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, 295c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 296c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 297c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!"); 298c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#ifndef NDEBUG 299c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman for (unsigned i = 0, e = Ops.size(); i != e; ++i) 300c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); 301c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman#endif 302e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineBasicBlock &MBB = *MI->getParent(); 303e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineFunction &MF = *MBB.getParent(); 304c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 305c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Ask the target to do the actual folding. 306c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI); 307c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman if (!NewMI) return 0; 308c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 309e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen NewMI = MBB.insert(MI, NewMI); 310e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen 311c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman // Copy the memoperands from the load to the folded instruction. 312c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman NewMI->setMemRefs(LoadMI->memoperands_begin(), 313c76909abfec876c6b751d693ebd3df07df686aa0Dan Gohman LoadMI->memoperands_end()); 314c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 315c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return NewMI; 316c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman} 317a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 31844acc24117b1a9eafb7b9b993731ca0115569ea2Evan Chengbool TargetInstrInfo:: 31944acc24117b1a9eafb7b9b993731ca0115569ea2Evan ChengisReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 32044acc24117b1a9eafb7b9b993731ca0115569ea2Evan Cheng AliasAnalysis *AA) const { 321a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineFunction &MF = *MI->getParent()->getParent(); 322a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineRegisterInfo &MRI = MF.getRegInfo(); 323a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetMachine &TM = MF.getTarget(); 324a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrInfo &TII = *TM.getInstrInfo(); 325a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 326a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 327a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A load from a fixed stack slot can be rematerialized. This may be 328a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // redundant with subsequent checks, but it's target-independent, 329a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // simple, and a common case. 330a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman int FrameIdx = 0; 331a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TII.isLoadFromStackSlot(MI, FrameIdx) && 332a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx)) 333a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 334a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 335a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const TargetInstrDesc &TID = MI->getDesc(); 336a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 337a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions obviously unsafe for remat. 338c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng if (TID.isNotDuplicable() || TID.mayStore() || 339c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng MI->hasUnmodeledSideEffects()) 340c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng return false; 341c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng 342c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // Don't remat inline asm. We have no idea how expensive it is 343c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng // even if it's side effect free. 344c36b7069b42bece963b7e6adf020353ce990ef76Evan Cheng if (MI->isInlineAsm()) 345a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 346a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 347a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Avoid instructions which load from potentially varying memory. 348a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TID.mayLoad() && !MI->isInvariantLoad(AA)) 349a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 350a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 351a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If any of the registers accessed are non-constant, conservatively assume 352a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // the instruction is not rematerializable. 353a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 354a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman const MachineOperand &MO = MI->getOperand(i); 355a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MO.isReg()) continue; 356a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned Reg = MO.getReg(); 357a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (Reg == 0) 358a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 359a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 360a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a well-behaved physical register. 361a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 362a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) { 363a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // If the physreg has no defs anywhere, it's just an ambient register 364a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // and we can freely move its uses. Alternatively, if it's allocatable, 365a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // it could get allocated to something with a def during allocation. 366a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(Reg)) 367a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 368a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0); 369a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(Reg)) 370a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 371a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Check for a def among the register's aliases too. 372a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) { 373a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman unsigned AliasReg = *Alias; 374a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (!MRI.def_empty(AliasReg)) 375a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 376a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (AllocatableRegs.test(AliasReg)) 377a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 378a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 379a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } else { 380a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // A physreg def. We can't remat it. 381a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 382a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 383a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman continue; 384a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 385a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 386a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Only allow one virtual-register def, and that in the first operand. 387a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isDef() != (i == 0)) 388a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 389a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 390a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Don't allow any virtual-register uses. Rematting an instruction with 391a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // virtual register uses would length the live ranges of the uses, which 392a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // is not necessarily a good idea, certainly not "trivial". 393a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman if (MO.isUse()) 394a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 395a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman } 396a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 397a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman // Everything checked out. 398a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return true; 399a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman} 400774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng 40186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// isSchedulingBoundary - Test if the given instruction should be 40286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// considered a scheduling boundary. This primarily includes labels 40386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng/// and terminators. 40486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Chengbool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI, 40586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 40686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const{ 40786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Terminators and labels can't be scheduled around. 40886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->getDesc().isTerminator() || MI->isLabel()) 40986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 41086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 41186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // Don't attempt to schedule around any instruction that defines 41286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // a stack-oriented pointer, as it's unlikely to be profitable. This 41386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // saves compile time, because it doesn't require every single 41486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // stack slot reference to depend on the instruction that does the 41586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng // modification. 41686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); 41786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore())) 41886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return true; 41986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 42086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng return false; 42186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng} 42286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 423c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick// Provide a global flag for disabling the PreRA hazard recognizer that targets 424c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick// may choose to honor. 425c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trickbool TargetInstrInfoImpl::usePreRAHazardRecognizer() const { 426c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return !DisableHazardRecognizer; 427c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick} 428c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 429c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick// Default implementation of CreateTargetRAHazardRecognizer. 4302da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *TargetInstrInfoImpl:: 4312da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetHazardRecognizer(const TargetMachine *TM, 4322da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 4332da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick // Dummy hazard recognizer allows all instructions to issue. 4342da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return new ScheduleHazardRecognizer(); 4352da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 4362da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 437774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng// Default implementation of CreateTargetPostRAHazardRecognizer. 438774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan ChengScheduleHazardRecognizer *TargetInstrInfoImpl:: 4392da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickCreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 4402da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 4412da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick return (ScheduleHazardRecognizer *) 4422da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched"); 443774bc882fdb3bbb0558075360c6e5bc510a0bdadEvan Cheng} 444