Thumb1RegisterInfo.cpp revision 5f366af2ff36cc65fe4964194b07bf1455828ff0 
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "Thumb1InstrInfo.h"
21#include "Thumb1RegisterInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/Target/TargetFrameInfo.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
41                                       const ARMSubtarget &sti)
42  : ARMBaseRegisterInfo(tii, sti) {
43}
44
45/// emitLoadConstPool - Emits a load from constpool to materialize the
46/// specified immediate.
47void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
48                                           MachineBasicBlock::iterator &MBBI,
49                                           DebugLoc dl,
50                                           unsigned DestReg, unsigned SubIdx,
51                                           int Val,
52                                           ARMCC::CondCodes Pred,
53                                           unsigned PredReg) const {
54  MachineFunction &MF = *MBB.getParent();
55  MachineConstantPool *ConstantPool = MF.getConstantPool();
56  Constant *C = ConstantInt::get(
57          Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
58  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
59
60  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
61          .addReg(DestReg, getDefRegState(true), SubIdx)
62          .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
63}
64
65const TargetRegisterClass*
66Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
67  if (isARMLowRegister(Reg))
68    return ARM::tGPRRegisterClass;
69  switch (Reg) {
70   default:
71    break;
72   case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
73   case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
74    return ARM::GPRRegisterClass;
75  }
76
77  return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
78}
79
80bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
81  const MachineFrameInfo *FFI = MF.getFrameInfo();
82  unsigned CFSize = FFI->getMaxCallFrameSize();
83  // It's not always a good idea to include the call frame as part of the
84  // stack frame. ARM (especially Thumb) has small immediate offset to
85  // address the stack frame. So a large call frame can cause poor codegen
86  // and may even makes it impossible to scavenge a register.
87  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
88    return false;
89
90  return !MF.getFrameInfo()->hasVarSizedObjects();
91}
92
93
94/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
95/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
96/// in a register using mov / mvn sequences or load the immediate from a
97/// constpool entry.
98static
99void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
100                              MachineBasicBlock::iterator &MBBI,
101                              unsigned DestReg, unsigned BaseReg,
102                              int NumBytes, bool CanChangeCC,
103                              const TargetInstrInfo &TII,
104                              const Thumb1RegisterInfo& MRI,
105                              DebugLoc dl) {
106    MachineFunction &MF = *MBB.getParent();
107    bool isHigh = !isARMLowRegister(DestReg) ||
108                  (BaseReg != 0 && !isARMLowRegister(BaseReg));
109    bool isSub = false;
110    // Subtract doesn't have high register version. Load the negative value
111    // if either base or dest register is a high register. Also, if do not
112    // issue sub as part of the sequence if condition register is to be
113    // preserved.
114    if (NumBytes < 0 && !isHigh && CanChangeCC) {
115      isSub = true;
116      NumBytes = -NumBytes;
117    }
118    unsigned LdReg = DestReg;
119    if (DestReg == ARM::SP) {
120      assert(BaseReg == ARM::SP && "Unexpected!");
121      LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
122    }
123
124    if (NumBytes <= 255 && NumBytes >= 0)
125      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
126        .addImm(NumBytes);
127    else if (NumBytes < 0 && NumBytes >= -255) {
128      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
129        .addImm(NumBytes);
130      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
131        .addReg(LdReg, RegState::Kill);
132    } else
133      MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
134
135    // Emit add / sub.
136    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
137    MachineInstrBuilder MIB =
138      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
139    if (Opc != ARM::tADDhirr)
140      MIB = AddDefaultT1CC(MIB);
141    if (DestReg == ARM::SP || isSub)
142      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
143    else
144      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
145    AddDefaultPred(MIB);
146}
147
148/// calcNumMI - Returns the number of instructions required to materialize
149/// the specific add / sub r, c instruction.
150static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
151                          unsigned NumBits, unsigned Scale) {
152  unsigned NumMIs = 0;
153  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
154
155  if (Opc == ARM::tADDrSPi) {
156    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
157    Bytes -= ThisVal;
158    NumMIs++;
159    NumBits = 8;
160    Scale = 1;  // Followed by a number of tADDi8.
161    Chunk = ((1 << NumBits) - 1) * Scale;
162  }
163
164  NumMIs += Bytes / Chunk;
165  if ((Bytes % Chunk) != 0)
166    NumMIs++;
167  if (ExtraOpc)
168    NumMIs++;
169  return NumMIs;
170}
171
172/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
173/// a destreg = basereg + immediate in Thumb code.
174static
175void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
176                               MachineBasicBlock::iterator &MBBI,
177                               unsigned DestReg, unsigned BaseReg,
178                               int NumBytes, const TargetInstrInfo &TII,
179                               const Thumb1RegisterInfo& MRI,
180                               DebugLoc dl) {
181  bool isSub = NumBytes < 0;
182  unsigned Bytes = (unsigned)NumBytes;
183  if (isSub) Bytes = -NumBytes;
184  bool isMul4 = (Bytes & 3) == 0;
185  bool isTwoAddr = false;
186  bool DstNotEqBase = false;
187  unsigned NumBits = 1;
188  unsigned Scale = 1;
189  int Opc = 0;
190  int ExtraOpc = 0;
191  bool NeedCC = false;
192  bool NeedPred = false;
193
194  if (DestReg == BaseReg && BaseReg == ARM::SP) {
195    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
196    NumBits = 7;
197    Scale = 4;
198    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
199    isTwoAddr = true;
200  } else if (!isSub && BaseReg == ARM::SP) {
201    // r1 = add sp, 403
202    // =>
203    // r1 = add sp, 100 * 4
204    // r1 = add r1, 3
205    if (!isMul4) {
206      Bytes &= ~3;
207      ExtraOpc = ARM::tADDi3;
208    }
209    NumBits = 8;
210    Scale = 4;
211    Opc = ARM::tADDrSPi;
212  } else {
213    // sp = sub sp, c
214    // r1 = sub sp, c
215    // r8 = sub sp, c
216    if (DestReg != BaseReg)
217      DstNotEqBase = true;
218    NumBits = 8;
219    if (DestReg == ARM::SP) {
220      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
221      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
222      NumBits = 7;
223      Scale = 4;
224    } else {
225      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
226      NumBits = 8;
227      NeedPred = NeedCC = true;
228    }
229    isTwoAddr = true;
230  }
231
232  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
233  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
234  if (NumMIs > Threshold) {
235    // This will expand into too many instructions. Load the immediate from a
236    // constpool entry.
237    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
238                             MRI, dl);
239    return;
240  }
241
242  if (DstNotEqBase) {
243    if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
244      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
245      unsigned Chunk = (1 << 3) - 1;
246      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
247      Bytes -= ThisVal;
248      const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
249      const MachineInstrBuilder MIB =
250        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
251      AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
252    } else {
253      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
254        .addReg(BaseReg, RegState::Kill);
255    }
256    BaseReg = DestReg;
257  }
258
259  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
260  while (Bytes) {
261    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
262    Bytes -= ThisVal;
263    ThisVal /= Scale;
264    // Build the new tADD / tSUB.
265    if (isTwoAddr) {
266      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
267      if (NeedCC)
268        MIB = AddDefaultT1CC(MIB);
269      MIB .addReg(DestReg).addImm(ThisVal);
270      if (NeedPred)
271        MIB = AddDefaultPred(MIB);
272    }
273    else {
274      bool isKill = BaseReg != ARM::SP;
275      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
276      if (NeedCC)
277        MIB = AddDefaultT1CC(MIB);
278      MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
279      if (NeedPred)
280        MIB = AddDefaultPred(MIB);
281      BaseReg = DestReg;
282
283      if (Opc == ARM::tADDrSPi) {
284        // r4 = add sp, imm
285        // r4 = add r4, imm
286        // ...
287        NumBits = 8;
288        Scale = 1;
289        Chunk = ((1 << NumBits) - 1) * Scale;
290        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
291        NeedPred = NeedCC = isTwoAddr = true;
292      }
293    }
294  }
295
296  if (ExtraOpc) {
297    const TargetInstrDesc &TID = TII.get(ExtraOpc);
298    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
299                   .addReg(DestReg, RegState::Kill)
300                   .addImm(((unsigned)NumBytes) & 3));
301  }
302}
303
304static void emitSPUpdate(MachineBasicBlock &MBB,
305                         MachineBasicBlock::iterator &MBBI,
306                         const TargetInstrInfo &TII, DebugLoc dl,
307                         const Thumb1RegisterInfo &MRI,
308                         int NumBytes) {
309  emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
310                            MRI, dl);
311}
312
313void Thumb1RegisterInfo::
314eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
315                              MachineBasicBlock::iterator I) const {
316  if (!hasReservedCallFrame(MF)) {
317    // If we have alloca, convert as follows:
318    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
319    // ADJCALLSTACKUP   -> add, sp, sp, amount
320    MachineInstr *Old = I;
321    DebugLoc dl = Old->getDebugLoc();
322    unsigned Amount = Old->getOperand(0).getImm();
323    if (Amount != 0) {
324      // We need to keep the stack aligned properly.  To do this, we round the
325      // amount of space needed for the outgoing arguments up to the next
326      // alignment boundary.
327      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
328      Amount = (Amount+Align-1)/Align*Align;
329
330      // Replace the pseudo instruction with a new instruction...
331      unsigned Opc = Old->getOpcode();
332      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
333        emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
334      } else {
335        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
336        emitSPUpdate(MBB, I, TII, dl, *this, Amount);
337      }
338    }
339  }
340  MBB.erase(I);
341}
342
343/// emitThumbConstant - Emit a series of instructions to materialize a
344/// constant.
345static void emitThumbConstant(MachineBasicBlock &MBB,
346                              MachineBasicBlock::iterator &MBBI,
347                              unsigned DestReg, int Imm,
348                              const TargetInstrInfo &TII,
349                              const Thumb1RegisterInfo& MRI,
350                              DebugLoc dl) {
351  bool isSub = Imm < 0;
352  if (isSub) Imm = -Imm;
353
354  int Chunk = (1 << 8) - 1;
355  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
356  Imm -= ThisVal;
357  AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
358                                        DestReg))
359                 .addImm(ThisVal));
360  if (Imm > 0)
361    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
362  if (isSub) {
363    const TargetInstrDesc &TID = TII.get(ARM::tRSB);
364    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
365                   .addReg(DestReg, RegState::Kill));
366  }
367}
368
369static void removeOperands(MachineInstr &MI, unsigned i) {
370  unsigned Op = i;
371  for (unsigned e = MI.getNumOperands(); i != e; ++i)
372    MI.RemoveOperand(Op);
373}
374
375int Thumb1RegisterInfo::
376rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
377                  unsigned FrameReg, int Offset,
378                  unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
379{
380  // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
381  // version then can pull out Thumb1 specific parts here
382  return 0;
383}
384
385/// saveScavengerRegister - Spill the register so it can be used by the
386/// register scavenger. Return true.
387bool
388Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
389                                          MachineBasicBlock::iterator I,
390                                          MachineBasicBlock::iterator &UseMI,
391                                          const TargetRegisterClass *RC,
392                                          unsigned Reg) const {
393  // Thumb1 can't use the emergency spill slot on the stack because
394  // ldr/str immediate offsets must be positive, and if we're referencing
395  // off the frame pointer (if, for example, there are alloca() calls in
396  // the function, the offset will be negative. Use R12 instead since that's
397  // a call clobbered register that we know won't be used in Thumb1 mode.
398  DebugLoc DL = DebugLoc::getUnknownLoc();
399  BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
400    addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
401
402  // The UseMI is where we would like to restore the register. If there's
403  // interference with R12 before then, however, we'll need to restore it
404  // before that instead and adjust the UseMI.
405  bool done = false;
406  for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
407    // If this instruction affects R12, adjust our restore point.
408    for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
409      const MachineOperand &MO = II->getOperand(i);
410      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
411          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
412        continue;
413      if (MO.getReg() == ARM::R12) {
414        UseMI = II;
415        done = true;
416        break;
417      }
418    }
419  }
420  // Restore the register from R12
421  BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
422    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
423
424  return true;
425}
426
427unsigned
428Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
429                                        int SPAdj, int *Value,
430                                        RegScavenger *RS) const{
431  unsigned VReg = 0;
432  unsigned i = 0;
433  MachineInstr &MI = *II;
434  MachineBasicBlock &MBB = *MI.getParent();
435  MachineFunction &MF = *MBB.getParent();
436  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
437  DebugLoc dl = MI.getDebugLoc();
438
439  while (!MI.getOperand(i).isFI()) {
440    ++i;
441    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
442  }
443
444  unsigned FrameReg = ARM::SP;
445  int FrameIndex = MI.getOperand(i).getIndex();
446  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
447               MF.getFrameInfo()->getStackSize() + SPAdj;
448
449  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
450    Offset -= AFI->getGPRCalleeSavedArea1Offset();
451  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
452    Offset -= AFI->getGPRCalleeSavedArea2Offset();
453  else if (MF.getFrameInfo()->hasVarSizedObjects()) {
454    assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
455    // There are alloca()'s in this function, must reference off the frame
456    // pointer instead.
457    FrameReg = getFrameRegister(MF);
458    Offset -= AFI->getFramePtrSpillOffset();
459  }
460
461  unsigned Opcode = MI.getOpcode();
462  const TargetInstrDesc &Desc = MI.getDesc();
463  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
464
465  if (Opcode == ARM::tADDrSPi) {
466    Offset += MI.getOperand(i+1).getImm();
467
468    // Can't use tADDrSPi if it's based off the frame pointer.
469    unsigned NumBits = 0;
470    unsigned Scale = 1;
471    if (FrameReg != ARM::SP) {
472      Opcode = ARM::tADDi3;
473      MI.setDesc(TII.get(Opcode));
474      NumBits = 3;
475    } else {
476      NumBits = 8;
477      Scale = 4;
478      assert((Offset & 3) == 0 &&
479             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
480    }
481
482    unsigned PredReg;
483    if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
484      // Turn it into a move.
485      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
486      MI.getOperand(i).ChangeToRegister(FrameReg, false);
487      // Remove offset and remaining explicit predicate operands.
488      do MI.RemoveOperand(i+1);
489      while (MI.getNumOperands() > i+1 &&
490             (!MI.getOperand(i+1).isReg() || !MI.getOperand(i+1).isImm()));
491      return 0;
492    }
493
494    // Common case: small offset, fits into instruction.
495    unsigned Mask = (1 << NumBits) - 1;
496    if (((Offset / Scale) & ~Mask) == 0) {
497      // Replace the FrameIndex with sp / fp
498      if (Opcode == ARM::tADDi3) {
499        removeOperands(MI, i);
500        MachineInstrBuilder MIB(&MI);
501        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
502                       .addImm(Offset / Scale));
503      } else {
504        MI.getOperand(i).ChangeToRegister(FrameReg, false);
505        MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
506      }
507      return 0;
508    }
509
510    unsigned DestReg = MI.getOperand(0).getReg();
511    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
512    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
513    // MI would expand into a large number of instructions. Don't try to
514    // simplify the immediate.
515    if (NumMIs > 2) {
516      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
517                                *this, dl);
518      MBB.erase(II);
519      return 0;
520    }
521
522    if (Offset > 0) {
523      // Translate r0 = add sp, imm to
524      // r0 = add sp, 255*4
525      // r0 = add r0, (imm - 255*4)
526      if (Opcode == ARM::tADDi3) {
527        removeOperands(MI, i);
528        MachineInstrBuilder MIB(&MI);
529        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
530      } else {
531        MI.getOperand(i).ChangeToRegister(FrameReg, false);
532        MI.getOperand(i+1).ChangeToImmediate(Mask);
533      }
534      Offset = (Offset - Mask * Scale);
535      MachineBasicBlock::iterator NII = llvm::next(II);
536      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
537                                *this, dl);
538    } else {
539      // Translate r0 = add sp, -imm to
540      // r0 = -imm (this is then translated into a series of instructons)
541      // r0 = add r0, sp
542      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
543
544      MI.setDesc(TII.get(ARM::tADDhirr));
545      MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
546      MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
547      if (Opcode == ARM::tADDi3) {
548        MachineInstrBuilder MIB(&MI);
549        AddDefaultPred(MIB);
550      }
551    }
552    return 0;
553  } else {
554    unsigned ImmIdx = 0;
555    int InstrOffs = 0;
556    unsigned NumBits = 0;
557    unsigned Scale = 1;
558    switch (AddrMode) {
559    case ARMII::AddrModeT1_s: {
560      ImmIdx = i+1;
561      InstrOffs = MI.getOperand(ImmIdx).getImm();
562      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
563      Scale = 4;
564      break;
565    }
566    default:
567      llvm_unreachable("Unsupported addressing mode!");
568      break;
569    }
570
571    Offset += InstrOffs * Scale;
572    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
573
574    // Common case: small offset, fits into instruction.
575    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
576    int ImmedOffset = Offset / Scale;
577    unsigned Mask = (1 << NumBits) - 1;
578    if ((unsigned)Offset <= Mask * Scale) {
579      // Replace the FrameIndex with sp
580      MI.getOperand(i).ChangeToRegister(FrameReg, false);
581      ImmOp.ChangeToImmediate(ImmedOffset);
582      return 0;
583    }
584
585    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
586    if (AddrMode == ARMII::AddrModeT1_s) {
587      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
588      // a different base register.
589      NumBits = 5;
590      Mask = (1 << NumBits) - 1;
591    }
592    // If this is a thumb spill / restore, we will be using a constpool load to
593    // materialize the offset.
594    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
595      ImmOp.ChangeToImmediate(0);
596    else {
597      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
598      ImmedOffset = ImmedOffset & Mask;
599      ImmOp.ChangeToImmediate(ImmedOffset);
600      Offset &= ~(Mask*Scale);
601    }
602  }
603
604  // If we get here, the immediate doesn't fit into the instruction.  We folded
605  // as much as possible above, handle the rest, providing a register that is
606  // SP+LargeImm.
607  assert(Offset && "This code isn't needed if offset already handled!");
608
609  // Remove predicate first.
610  int PIdx = MI.findFirstPredOperandIdx();
611  if (PIdx != -1)
612    removeOperands(MI, PIdx);
613
614  if (Desc.mayLoad()) {
615    // Use the destination register to materialize sp + offset.
616    unsigned TmpReg = MI.getOperand(0).getReg();
617    bool UseRR = false;
618    if (Opcode == ARM::tRestore) {
619      if (FrameReg == ARM::SP)
620        emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
621                                 Offset, false, TII, *this, dl);
622      else {
623        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
624        UseRR = true;
625      }
626    } else {
627      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
628                                *this, dl);
629    }
630
631    MI.setDesc(TII.get(ARM::tLDR));
632    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
633    if (UseRR)
634      // Use [reg, reg] addrmode.
635      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
636    else  // tLDR has an extra register operand.
637      MI.addOperand(MachineOperand::CreateReg(0, false));
638  } else if (Desc.mayStore()) {
639      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
640      assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
641      *Value = Offset;
642      bool UseRR = false;
643
644      if (Opcode == ARM::tSpill) {
645        if (FrameReg == ARM::SP)
646          emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
647                                   Offset, false, TII, *this, dl);
648        else {
649          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
650          UseRR = true;
651        }
652      } else
653        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
654                                  *this, dl);
655      MI.setDesc(TII.get(ARM::tSTR));
656      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
657      if (UseRR)  // Use [reg, reg] addrmode.
658        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
659      else // tSTR has an extra register operand.
660        MI.addOperand(MachineOperand::CreateReg(0, false));
661  } else
662    assert(false && "Unexpected opcode!");
663
664  // Add predicate back if it's needed.
665  if (MI.getDesc().isPredicable()) {
666    MachineInstrBuilder MIB(&MI);
667    AddDefaultPred(MIB);
668  }
669  return VReg;
670}
671
672void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
673  MachineBasicBlock &MBB = MF.front();
674  MachineBasicBlock::iterator MBBI = MBB.begin();
675  MachineFrameInfo  *MFI = MF.getFrameInfo();
676  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
677  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
678  unsigned NumBytes = MFI->getStackSize();
679  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
680  DebugLoc dl = (MBBI != MBB.end() ?
681                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
682
683  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
684  NumBytes = (NumBytes + 3) & ~3;
685  MFI->setStackSize(NumBytes);
686
687  // Determine the sizes of each callee-save spill areas and record which frame
688  // belongs to which callee-save spill areas.
689  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
690  int FramePtrSpillFI = 0;
691
692  if (VARegSaveSize)
693    emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
694
695  if (!AFI->hasStackFrame()) {
696    if (NumBytes != 0)
697      emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
698    return;
699  }
700
701  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
702    unsigned Reg = CSI[i].getReg();
703    int FI = CSI[i].getFrameIdx();
704    switch (Reg) {
705    case ARM::R4:
706    case ARM::R5:
707    case ARM::R6:
708    case ARM::R7:
709    case ARM::LR:
710      if (Reg == FramePtr)
711        FramePtrSpillFI = FI;
712      AFI->addGPRCalleeSavedArea1Frame(FI);
713      GPRCS1Size += 4;
714      break;
715    case ARM::R8:
716    case ARM::R9:
717    case ARM::R10:
718    case ARM::R11:
719      if (Reg == FramePtr)
720        FramePtrSpillFI = FI;
721      if (STI.isTargetDarwin()) {
722        AFI->addGPRCalleeSavedArea2Frame(FI);
723        GPRCS2Size += 4;
724      } else {
725        AFI->addGPRCalleeSavedArea1Frame(FI);
726        GPRCS1Size += 4;
727      }
728      break;
729    default:
730      AFI->addDPRCalleeSavedAreaFrame(FI);
731      DPRCSSize += 8;
732    }
733  }
734
735  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
736    ++MBBI;
737    if (MBBI != MBB.end())
738      dl = MBBI->getDebugLoc();
739  }
740
741  // Darwin ABI requires FP to point to the stack slot that contains the
742  // previous FP.
743  if (STI.isTargetDarwin() || hasFP(MF)) {
744    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
745      .addFrameIndex(FramePtrSpillFI).addImm(0);
746  }
747
748  // Determine starting offsets of spill areas.
749  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
750  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
751  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
752  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
753  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
754  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
755  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
756
757  NumBytes = DPRCSOffset;
758  if (NumBytes) {
759    // Insert it after all the callee-save spills.
760    emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
761  }
762
763  if (STI.isTargetELF() && hasFP(MF)) {
764    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
765                             AFI->getFramePtrSpillOffset());
766  }
767
768  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
769  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
770  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
771}
772
773static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
774  for (unsigned i = 0; CSRegs[i]; ++i)
775    if (Reg == CSRegs[i])
776      return true;
777  return false;
778}
779
780static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
781  return (MI->getOpcode() == ARM::tRestore &&
782          MI->getOperand(1).isFI() &&
783          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
784}
785
786void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
787                                      MachineBasicBlock &MBB) const {
788  MachineBasicBlock::iterator MBBI = prior(MBB.end());
789  assert((MBBI->getOpcode() == ARM::tBX_RET ||
790          MBBI->getOpcode() == ARM::tPOP_RET) &&
791         "Can only insert epilog into returning blocks");
792  DebugLoc dl = MBBI->getDebugLoc();
793  MachineFrameInfo *MFI = MF.getFrameInfo();
794  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
795  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
796  int NumBytes = (int)MFI->getStackSize();
797
798  if (!AFI->hasStackFrame()) {
799    if (NumBytes != 0)
800      emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
801  } else {
802    // Unwind MBBI to point to first LDR / VLDRD.
803    const unsigned *CSRegs = getCalleeSavedRegs();
804    if (MBBI != MBB.begin()) {
805      do
806        --MBBI;
807      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
808      if (!isCSRestore(MBBI, CSRegs))
809        ++MBBI;
810    }
811
812    // Move SP to start of FP callee save spill area.
813    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
814                 AFI->getGPRCalleeSavedArea2Size() +
815                 AFI->getDPRCalleeSavedAreaSize());
816
817    if (hasFP(MF)) {
818      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
819      // Reset SP based on frame pointer only if the stack frame extends beyond
820      // frame pointer stack slot or target is ELF and the function has FP.
821      if (NumBytes)
822        emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
823                                  TII, *this, dl);
824      else
825        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
826          .addReg(FramePtr);
827    } else {
828      if (MBBI->getOpcode() == ARM::tBX_RET &&
829          &MBB.front() != MBBI &&
830          prior(MBBI)->getOpcode() == ARM::tPOP) {
831        MachineBasicBlock::iterator PMBBI = prior(MBBI);
832        emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
833      } else
834        emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
835    }
836  }
837
838  if (VARegSaveSize) {
839    // Epilogue for vararg functions: pop LR to R3 and branch off it.
840    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
841      .addReg(0) // No write back.
842      .addReg(ARM::R3, RegState::Define);
843
844    emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
845
846    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
847      .addReg(ARM::R3, RegState::Kill);
848    MBB.erase(MBBI);
849  }
850}
851