SPUISelLowering.h revision 21213e75b57f87182cbfa7cd8f55a37bcb7c4097 
1//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Cell SPU uses to lower LLVM code into
11// a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPU_ISELLOWERING_H
16#define SPU_ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "SPU.h"
21
22namespace llvm {
23  namespace SPUISD {
24    enum NodeType {
25      // Start the numbering where the builting ops and target ops leave off.
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28      // Pseudo instructions:
29      RET_FLAG,                 ///< Return with flag, matched by bi instruction
30
31      Hi,                       ///< High address component (upper 16)
32      Lo,                       ///< Low address component (lower 16)
33      PCRelAddr,                ///< Program counter relative address
34      AFormAddr,                ///< A-form address (local store)
35      IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
36
37      LDRESULT,                 ///< Load result (value, chain)
38      CALL,                     ///< CALL instruction
39      SHUFB,                    ///< Vector shuffle (permute)
40      SHUFFLE_MASK,             ///< Shuffle mask
41      CNTB,                     ///< Count leading ones in bytes
42      PREFSLOT2VEC,             ///< Promote scalar->vector
43      VEC2PREFSLOT,             ///< Extract element 0
44      SHLQUAD_L_BITS,           ///< Rotate quad left, by bits
45      SHLQUAD_L_BYTES,          ///< Rotate quad left, by bytes
46      VEC_SHL,                  ///< Vector shift left
47      VEC_SRL,                  ///< Vector shift right (logical)
48      VEC_SRA,                  ///< Vector shift right (arithmetic)
49      VEC_ROTL,                 ///< Vector rotate left
50      VEC_ROTR,                 ///< Vector rotate right
51      ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
52      ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
53      SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
54      SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
55      ADD_EXTENDED,             ///< Add extended, with carry
56      CARRY_GENERATE,           ///< Carry generate for ADD_EXTENDED
57      SUB_EXTENDED,             ///< Subtract extended, with borrow
58      BORROW_GENERATE,          ///< Borrow generate for SUB_EXTENDED
59      LAST_SPUISD               ///< Last user-defined instruction
60    };
61  }
62
63  /// Predicates that are used for node matching:
64  namespace SPU {
65    SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66                             MVT ValueType);
67    SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68                             MVT ValueType);
69    SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70                             MVT ValueType);
71    SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72                            MVT ValueType);
73    SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74                              MVT ValueType);
75    SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
76    SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
77  }
78
79  class SPUTargetMachine;            // forward dec'l.
80
81  class SPUTargetLowering :
82    public TargetLowering
83  {
84    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
85    int ReturnAddrIndex;              // FrameIndex for return slot.
86    SPUTargetMachine &SPUTM;
87
88  public:
89    SPUTargetLowering(SPUTargetMachine &TM);
90
91    /// getTargetNodeName() - This method returns the name of a target specific
92    /// DAG node.
93    virtual const char *getTargetNodeName(unsigned Opcode) const;
94
95    /// getSetCCResultType - Return the ValueType for ISD::SETCC
96    virtual MVT getSetCCResultType(MVT VT) const;
97
98    //! Custom lowering hooks
99    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
100
101    //! Custom lowering hook for nodes with illegal result types.
102    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
103                                    SelectionDAG &DAG);
104
105    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
106
107    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
108                                                const APInt &Mask,
109                                                APInt &KnownZero,
110                                                APInt &KnownOne,
111                                                const SelectionDAG &DAG,
112                                                unsigned Depth = 0) const;
113
114    virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
115                                                   unsigned Depth = 0) const;
116
117    ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
118
119    std::pair<unsigned, const TargetRegisterClass*>
120      getRegForInlineAsmConstraint(const std::string &Constraint,
121                                   MVT VT) const;
122
123    void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
124                                      bool hasMemory,
125                                      std::vector<SDValue> &Ops,
126                                      SelectionDAG &DAG) const;
127
128    /// isLegalAddressImmediate - Return true if the integer value can be used
129    /// as the offset of the target addressing mode.
130    virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
131    virtual bool isLegalAddressImmediate(GlobalValue *) const;
132
133    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
134  };
135}
136
137#endif
138