SPUISelLowering.h revision 266bc8f7774b153401e54ed537db299159840981 
1//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by a team from the Computer Systems Research
6// Department at The Aerospace Corporation.
7//
8// See README.txt for details.
9//
10//===----------------------------------------------------------------------===//
11//
12// This file defines the interfaces that Cell SPU uses to lower LLVM code into
13// a selection DAG.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef SPU_ISELLOWERING_H
18#define SPU_ISELLOWERING_H
19
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "SPU.h"
23
24namespace llvm {
25  namespace SPUISD {
26    enum NodeType {
27      // Start the numbering where the builting ops and target ops leave off.
28      FIRST_NUMBER = ISD::BUILTIN_OP_END+SPU::INSTRUCTION_LIST_END,
29
30      // Pseudo instructions:
31      RET_FLAG,                 ///< Return with flag, matched by bi instruction
32
33      Hi,                       ///< High address component (upper 16)
34      Lo,                       ///< Low address component (lower 16)
35      PCRelAddr,                ///< Program counter relative address
36      DFormAddr,                ///< D-Form address "imm($r)"
37      XFormAddr,		///< X-Form address "$r1($r2)"
38
39      LDRESULT,                 ///< Load result (value, chain)
40      CALL,                     ///< CALL instruction
41      SHUFB,                    ///< Vector shuffle (permute)
42      INSERT_MASK,              ///< Insert element shuffle mask
43      CNTB,			///< Count leading ones in bytes
44      PROMOTE_SCALAR,           ///< Promote scalar->vector
45      EXTRACT_ELT0,             ///< Extract element 0
46      EXTRACT_ELT0_CHAINED,	///< Extract element 0, with chain
47      EXTRACT_I1_ZEXT,          ///< Extract element 0 as i1, zero extend
48      EXTRACT_I1_SEXT,          ///< Extract element 0 as i1, sign extend
49      EXTRACT_I8_ZEXT,          ///< Extract element 0 as i8, zero extend
50      EXTRACT_I8_SEXT,          ///< Extract element 0 as i8, sign extend
51      MPY,			///< 16-bit Multiply (low parts of a 32-bit)
52      MPYU,			///< Multiply Unsigned
53      MPYH,			///< Multiply High
54      MPYHH,			///< Multiply High-High
55      VEC_SHL,			///< Vector shift left
56      VEC_SRL,			///< Vector shift right (logical)
57      VEC_SRA,			///< Vector shift right (arithmetic)
58      VEC_ROTL,			///< Vector rotate left
59      VEC_ROTR,			///< Vector rotate right
60      ROTBYTES_RIGHT_Z,		///< Vector rotate right, by bytes, zero fill
61      ROTBYTES_RIGHT_S,         ///< Vector rotate right, by bytes, sign fill
62      ROTBYTES_LEFT,		///< Rotate bytes (loads -> ROTQBYI)
63      ROTBYTES_LEFT_CHAINED,	///< Rotate bytes (loads -> ROTQBYI), with chain
64      FSMBI,			///< Form Select Mask for Bytes, Immediate
65      SELB,			///< Select bits -> (b & mask) | (a & ~mask)
66      SFPConstant,		///< Single precision floating point constant
67      FPInterp,                 ///< Floating point interpolate
68      FPRecipEst,		///< Floating point reciprocal estimate
69      SEXT32TO64,		///< Sign-extended 32-bit const -> 64-bits
70      LAST_SPUISD		///< Last user-defined instruction
71    };
72  }
73
74  /// Predicates that are used for node matching:
75  namespace SPU {
76    SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
77                             MVT::ValueType ValueType);
78    SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
79                             MVT::ValueType ValueType);
80    SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
81                             MVT::ValueType ValueType);
82    SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
83                            MVT::ValueType ValueType);
84    SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
85                              MVT::ValueType ValueType);
86    SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
87    SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
88  }
89
90  class SPUTargetMachine;            // forward dec'l.
91
92  class SPUTargetLowering :
93    public TargetLowering
94  {
95    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
96    int ReturnAddrIndex;              // FrameIndex for return slot.
97    SPUTargetMachine &SPUTM;
98
99  public:
100    SPUTargetLowering(SPUTargetMachine &TM);
101
102    /// getTargetNodeName() - This method returns the name of a target specific
103    /// DAG node.
104    virtual const char *getTargetNodeName(unsigned Opcode) const;
105
106    /// LowerOperation - Provide custom lowering hooks for some operations.
107    ///
108    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
109
110    virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111
112    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
113                                                uint64_t Mask,
114                                                uint64_t &KnownZero,
115                                                uint64_t &KnownOne,
116                                                const SelectionDAG &DAG,
117                                                unsigned Depth = 0) const;
118
119    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
120                                                       MachineBasicBlock *MBB);
121
122    ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
123
124    std::pair<unsigned, const TargetRegisterClass*>
125      getRegForInlineAsmConstraint(const std::string &Constraint,
126                                   MVT::ValueType VT) const;
127
128    void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
129                                      std::vector<SDOperand> &Ops,
130                                      SelectionDAG &DAG);
131
132    /// isLegalAddressImmediate - Return true if the integer value can be used
133    /// as the offset of the target addressing mode.
134    virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
135    virtual bool isLegalAddressImmediate(GlobalValue *) const;
136  };
137}
138
139#endif
140