SPUISelLowering.h revision a59d469e9b31087f0f045bcb5d1a154c963be9b7 
1//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Cell SPU uses to lower LLVM code into
11// a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPU_ISELLOWERING_H
16#define SPU_ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "SPU.h"
21
22namespace llvm {
23  namespace SPUISD {
24    enum NodeType {
25      // Start the numbering where the builting ops and target ops leave off.
26      FIRST_NUMBER = ISD::BUILTIN_OP_END+SPU::INSTRUCTION_LIST_END,
27
28      // Pseudo instructions:
29      RET_FLAG,                 ///< Return with flag, matched by bi instruction
30
31      Hi,                       ///< High address component (upper 16)
32      Lo,                       ///< Low address component (lower 16)
33      PCRelAddr,                ///< Program counter relative address
34      AFormAddr,                ///< A-form address (local store)
35      IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
36
37      LDRESULT,                 ///< Load result (value, chain)
38      CALL,                     ///< CALL instruction
39      SHUFB,                    ///< Vector shuffle (permute)
40      INSERT_MASK,              ///< Insert element shuffle mask
41      CNTB,                     ///< Count leading ones in bytes
42      PROMOTE_SCALAR,           ///< Promote scalar->vector
43      EXTRACT_ELT0,             ///< Extract element 0
44      EXTRACT_ELT0_CHAINED,     ///< Extract element 0, with chain
45      EXTRACT_I1_ZEXT,          ///< Extract element 0 as i1, zero extend
46      EXTRACT_I1_SEXT,          ///< Extract element 0 as i1, sign extend
47      EXTRACT_I8_ZEXT,          ///< Extract element 0 as i8, zero extend
48      EXTRACT_I8_SEXT,          ///< Extract element 0 as i8, sign extend
49      MPY,                      ///< 16-bit Multiply (low parts of a 32-bit)
50      MPYU,                     ///< Multiply Unsigned
51      MPYH,                     ///< Multiply High
52      MPYHH,                    ///< Multiply High-High
53      SHLQUAD_L_BITS,           ///< Rotate quad left, by bits
54      SHLQUAD_L_BYTES,          ///< Rotate quad left, by bytes
55      VEC_SHL,                  ///< Vector shift left
56      VEC_SRL,                  ///< Vector shift right (logical)
57      VEC_SRA,                  ///< Vector shift right (arithmetic)
58      VEC_ROTL,                 ///< Vector rotate left
59      VEC_ROTR,                 ///< Vector rotate right
60      ROTQUAD_RZ_BYTES,         ///< Rotate quad right, by bytes, zero fill
61      ROTQUAD_RZ_BITS,          ///< Rotate quad right, by bits, zero fill
62      ROTBYTES_RIGHT_S,         ///< Vector rotate right, by bytes, sign fill
63      ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
64      ROTBYTES_LEFT_CHAINED,    ///< Rotate bytes (loads -> ROTQBYI), with chain
65      FSMBI,                    ///< Form Select Mask for Bytes, Immediate
66      SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
67      FPInterp,                 ///< Floating point interpolate
68      FPRecipEst,               ///< Floating point reciprocal estimate
69      SEXT32TO64,               ///< Sign-extended 32-bit const -> 64-bits
70      LAST_SPUISD               ///< Last user-defined instruction
71    };
72  }
73
74  /// Predicates that are used for node matching:
75  namespace SPU {
76    SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
77                             MVT::ValueType ValueType);
78    SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
79                             MVT::ValueType ValueType);
80    SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
81                             MVT::ValueType ValueType);
82    SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
83                            MVT::ValueType ValueType);
84    SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
85                              MVT::ValueType ValueType);
86    SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
87    SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
88  }
89
90  class SPUTargetMachine;            // forward dec'l.
91
92  class SPUTargetLowering :
93    public TargetLowering
94  {
95    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
96    int ReturnAddrIndex;              // FrameIndex for return slot.
97    SPUTargetMachine &SPUTM;
98
99  public:
100    SPUTargetLowering(SPUTargetMachine &TM);
101
102    /// getTargetNodeName() - This method returns the name of a target specific
103    /// DAG node.
104    virtual const char *getTargetNodeName(unsigned Opcode) const;
105
106    /// LowerOperation - Provide custom lowering hooks for some operations.
107    ///
108    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
109
110    virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111
112    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
113                                                const APInt &Mask,
114                                                APInt &KnownZero,
115                                                APInt &KnownOne,
116                                                const SelectionDAG &DAG,
117                                                unsigned Depth = 0) const;
118
119    ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
120
121    std::pair<unsigned, const TargetRegisterClass*>
122      getRegForInlineAsmConstraint(const std::string &Constraint,
123                                   MVT::ValueType VT) const;
124
125    void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
126                                      std::vector<SDOperand> &Ops,
127                                      SelectionDAG &DAG);
128
129    /// isLegalAddressImmediate - Return true if the integer value can be used
130    /// as the offset of the target addressing mode.
131    virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
132    virtual bool isLegalAddressImmediate(GlobalValue *) const;
133  };
134}
135
136#endif
137