HexagonInstrInfo.h revision ee498d3254b86bceb4f441741e9f442990647ce6
1b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum//=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=// 2b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 3b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// The LLVM Compiler Infrastructure 4b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 5b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// This file is distributed under the University of Illinois Open Source 6b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// License. See LICENSE.TXT for details. 7b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 8b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum//===----------------------------------------------------------------------===// 9b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 10b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// This file contains the Hexagon implementation of the TargetInstrInfo class. 11b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 12b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum//===----------------------------------------------------------------------===// 13b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 14b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#ifndef HexagonINSTRUCTIONINFO_H 15b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#define HexagonINSTRUCTIONINFO_H 16b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 17b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#include "llvm/Target/TargetInstrInfo.h" 18b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#include "llvm/Target/TargetFrameLowering.h" 19b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#include "HexagonRegisterInfo.h" 20b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 21b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 22b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#define GET_INSTRINFO_HEADER 23b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#include "HexagonGenInstrInfo.inc" 24b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 25b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicumnamespace llvm { 26b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 27b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicumclass HexagonInstrInfo : public HexagonGenInstrInfo { 28b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const HexagonRegisterInfo RI; 29b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const HexagonSubtarget& Subtarget; 30b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicumpublic: 31b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum explicit HexagonInstrInfo(HexagonSubtarget &ST); 32b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 33b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 34b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// such, whenever a client has an instance of instruction info, it should 35b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// always be able to get register info as well (through this method). 36b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// 37b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 38b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 39b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// isLoadFromStackSlot - If the specified machine instruction is a direct 40b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// load from a stack slot, return the virtual or physical register number of 41b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// the destination along with the FrameIndex of the loaded stack slot. If 42b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// not, return 0. This predicate must return 0 if the instruction has 43b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// any side effects other than loading from the stack slot. 44b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 45b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum int &FrameIndex) const; 46b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 47b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// isStoreToStackSlot - If the specified machine instruction is a direct 48b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// store to a stack slot, return the virtual or physical register number of 49b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// the source reg along with the FrameIndex of the loaded stack slot. If 50b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// not, return 0. This predicate must return 0 if the instruction has 51b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// any side effects other than storing to the stack slot. 52b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 53b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum int &FrameIndex) const; 54b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 55b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 56b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 57b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineBasicBlock *&FBB, 58b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum SmallVectorImpl<MachineOperand> &Cond, 59b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool AllowModify) const; 60b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 61b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 62b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 63b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 64b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineBasicBlock *FBB, 65b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const SmallVectorImpl<MachineOperand> &Cond, 66b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum DebugLoc DL) const; 67b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 68b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual void copyPhysReg(MachineBasicBlock &MBB, 69b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineBasicBlock::iterator I, DebugLoc DL, 70b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned DestReg, unsigned SrcReg, 71b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool KillSrc) const; 72b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 73b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 74b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineBasicBlock::iterator MBBI, 75b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned SrcReg, bool isKill, int FrameIndex, 76b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const TargetRegisterClass *RC, 77b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const TargetRegisterInfo *TRI) const; 78b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 79b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 80b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum SmallVectorImpl<MachineOperand> &Addr, 81b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const TargetRegisterClass *RC, 82b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum SmallVectorImpl<MachineInstr*> &NewMIs) const; 83b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 84b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 85b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineBasicBlock::iterator MBBI, 86b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned DestReg, int FrameIndex, 87b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const TargetRegisterClass *RC, 88b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const TargetRegisterInfo *TRI) const; 89b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 90b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 91b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum SmallVectorImpl<MachineOperand> &Addr, 92b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const TargetRegisterClass *RC, 93b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum SmallVectorImpl<MachineInstr*> &NewMIs) const; 94b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 95b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 96b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineInstr* MI, 97b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const SmallVectorImpl<unsigned> &Ops, 98b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum int FrameIndex) const; 99b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 100b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 101b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineInstr* MI, 102b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const SmallVectorImpl<unsigned> &Ops, 103b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineInstr* LoadMI) const { 104b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum return 0; 105b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum } 106b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 107b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned createVR(MachineFunction* MF, MVT VT) const; 108b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 109b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool isPredicable(MachineInstr *MI) const; 110b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool 111b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum PredicateInstruction(MachineInstr *MI, 112b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const SmallVectorImpl<MachineOperand> &Cond) const; 113b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 114b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 115b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned ExtraPredCycles, 116b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const BranchProbability &Probability) const; 117b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 118b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 119b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned NumTCycles, unsigned ExtraTCycles, 120b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum MachineBasicBlock &FMBB, 121b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned NumFCycles, unsigned ExtraFCycles, 122b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const BranchProbability &Probability) const; 123b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 124b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool isPredicated(const MachineInstr *MI) const; 125b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool DefinesPredicate(MachineInstr *MI, 126b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum std::vector<MachineOperand> &Pred) const; 127b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool 128b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 129b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const SmallVectorImpl<MachineOperand> &Pred2) const; 130b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 131b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool 132b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 133b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 134b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum virtual bool 135b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, 136b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum const BranchProbability &Probability) const; 137b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 138ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick virtual DFAPacketizer* 139ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick CreateTargetScheduleState(const TargetMachine *TM, 140ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick const ScheduleDAG *DAG) const; 141ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick 142ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick virtual bool isSchedulingBoundary(const MachineInstr *MI, 143ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick const MachineBasicBlock *MBB, 144ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick const MachineFunction &MF) const; 145b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isValidOffset(const int Opcode, const int Offset) const; 146b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isValidAutoIncImm(const EVT VT, const int Offset) const; 147b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isMemOp(const MachineInstr *MI) const; 148b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isSpillPredRegOp(const MachineInstr *MI) const; 149b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isU6_3Immediate(const int value) const; 150b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isU6_2Immediate(const int value) const; 151b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isU6_1Immediate(const int value) const; 152b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isU6_0Immediate(const int value) const; 153b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS4_3Immediate(const int value) const; 154b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS4_2Immediate(const int value) const; 155b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS4_1Immediate(const int value) const; 156b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS4_0Immediate(const int value) const; 157b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS12_Immediate(const int value) const; 158b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isU6_Immediate(const int value) const; 159b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS8_Immediate(const int value) const; 160b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isS6_Immediate(const int value) const; 161b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 162b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isConditionalALU32 (const MachineInstr* MI) const; 163b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isConditionalLoad (const MachineInstr* MI) const; 164b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum bool isDeallocRet(const MachineInstr *MI) const; 165b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 166b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicumprivate: 167b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum int getMatchingCondBranchOpcode(int Opc, bool sense) const; 168b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 169b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum}; 170b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 171b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum} 172b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 173b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#endif 174