MipsISelDAGToDAG.cpp revision b75673b6e18da3937e4cbcd944b081bdc28a6cf5 
1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MIPS target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "MCTargetDesc/MipsBaseInfo.h"
22#include "llvm/GlobalValue.h"
23#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/Support/CFG.h"
26#include "llvm/Type.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/SelectionDAGNodes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40//===----------------------------------------------------------------------===//
41// Instruction Selector Implementation
42//===----------------------------------------------------------------------===//
43
44//===----------------------------------------------------------------------===//
45// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46// instructions for SelectionDAG operations.
47//===----------------------------------------------------------------------===//
48namespace {
49
50class MipsDAGToDAGISel : public SelectionDAGISel {
51
52  /// TM - Keep a reference to MipsTargetMachine.
53  MipsTargetMachine &TM;
54
55  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56  /// make the right decision when generating code for different targets.
57  const MipsSubtarget &Subtarget;
58
59public:
60  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61  SelectionDAGISel(tm),
62  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63
64  // Pass Name
65  virtual const char *getPassName() const {
66    return "MIPS DAG->DAG Pattern Instruction Selection";
67  }
68
69  virtual bool runOnMachineFunction(MachineFunction &MF);
70
71private:
72  // Include the pieces autogenerated from the target description.
73  #include "MipsGenDAGISel.inc"
74
75  /// getTargetMachine - Return a reference to the TargetMachine, casted
76  /// to the target-specific type.
77  const MipsTargetMachine &getTargetMachine() {
78    return static_cast<const MipsTargetMachine &>(TM);
79  }
80
81  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82  /// to the target-specific type.
83  const MipsInstrInfo *getInstrInfo() {
84    return getTargetMachine().getInstrInfo();
85  }
86
87  SDNode *getGlobalBaseReg();
88
89  std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90                                         EVT Ty, bool HasLo, bool HasHi);
91
92  SDNode *Select(SDNode *N);
93
94  // Complex Pattern.
95  bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
96
97  // getImm - Return a target constant with the specified value.
98  inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99    return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
100  }
101
102  void InitGlobalBaseReg(MachineFunction &MF);
103
104  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
105                                            char ConstraintCode,
106                                            std::vector<SDValue> &OutOps);
107};
108
109}
110
111// Insert instructions to initialize the global base register in the
112// first MBB of the function. When the ABI is O32 and the relocation model is
113// PIC, the necessary instructions are emitted later to prevent optimization
114// passes from moving them.
115void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
116  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
117
118  if (!MipsFI->globalBaseRegSet())
119    return;
120
121  MachineBasicBlock &MBB = MF.front();
122  MachineBasicBlock::iterator I = MBB.begin();
123  MachineRegisterInfo &RegInfo = MF.getRegInfo();
124  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
125  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
126  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
127  bool FixGlobalBaseReg = MipsFI->globalBaseRegFixed();
128
129  if (Subtarget.isABI_O32() && FixGlobalBaseReg)
130    // $gp is the global base register.
131    V0 = V1 = GlobalBaseReg;
132  else {
133    const TargetRegisterClass *RC;
134    RC = Subtarget.isABI_N64() ?
135      Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
136
137    V0 = RegInfo.createVirtualRegister(RC);
138    V1 = RegInfo.createVirtualRegister(RC);
139  }
140
141  if (Subtarget.isABI_N64()) {
142    MF.getRegInfo().addLiveIn(Mips::T9_64);
143
144    // lui $v0, %hi(%neg(%gp_rel(fname)))
145    // daddu $v1, $v0, $t9
146    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
147    const GlobalValue *FName = MF.getFunction();
148    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
149      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
150    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
151    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
152      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
153  } else if (MF.getTarget().getRelocationModel() == Reloc::Static) {
154    // Set global register to __gnu_local_gp.
155    //
156    // lui   $v0, %hi(__gnu_local_gp)
157    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
158    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
159      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
160    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
161      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
162  } else {
163    MF.getRegInfo().addLiveIn(Mips::T9);
164
165    if (Subtarget.isABI_N32()) {
166      // lui $v0, %hi(%neg(%gp_rel(fname)))
167      // addu $v1, $v0, $t9
168      // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
169      const GlobalValue *FName = MF.getFunction();
170      BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
171        .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
172      BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
173      BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
174        .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
175    } else if (!MipsFI->globalBaseRegFixed()) {
176      assert(Subtarget.isABI_O32());
177
178      BuildMI(MBB, I, DL, TII.get(Mips::SETGP2), GlobalBaseReg)
179        .addReg(Mips::T9);
180    }
181  }
182}
183
184bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
185  bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
186
187  InitGlobalBaseReg(MF);
188
189  return Ret;
190}
191
192/// getGlobalBaseReg - Output the instructions required to put the
193/// GOT address into a register.
194SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
195  unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
196  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
197}
198
199/// ComplexPattern used on MipsInstrInfo
200/// Used on Mips Load/Store instructions
201bool MipsDAGToDAGISel::
202SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
203  EVT ValTy = Addr.getValueType();
204
205  // if Address is FI, get the TargetFrameIndex.
206  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
207    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
208    Offset = CurDAG->getTargetConstant(0, ValTy);
209    return true;
210  }
211
212  // on PIC code Load GA
213  if (Addr.getOpcode() == MipsISD::Wrapper) {
214    Base   = Addr.getOperand(0);
215    Offset = Addr.getOperand(1);
216    return true;
217  }
218
219  if (TM.getRelocationModel() != Reloc::PIC_) {
220    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
221        Addr.getOpcode() == ISD::TargetGlobalAddress))
222      return false;
223  }
224
225  // Addresses of the form FI+const or FI|const
226  if (CurDAG->isBaseWithConstantOffset(Addr)) {
227    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
228    if (isInt<16>(CN->getSExtValue())) {
229
230      // If the first operand is a FI, get the TargetFI Node
231      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
232                                  (Addr.getOperand(0)))
233        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
234      else
235        Base = Addr.getOperand(0);
236
237      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
238      return true;
239    }
240  }
241
242  // Operand is a result from an ADD.
243  if (Addr.getOpcode() == ISD::ADD) {
244    // When loading from constant pools, load the lower address part in
245    // the instruction itself. Example, instead of:
246    //  lui $2, %hi($CPI1_0)
247    //  addiu $2, $2, %lo($CPI1_0)
248    //  lwc1 $f0, 0($2)
249    // Generate:
250    //  lui $2, %hi($CPI1_0)
251    //  lwc1 $f0, %lo($CPI1_0)($2)
252    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
253      SDValue LoVal = Addr.getOperand(1);
254      if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
255          isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
256        Base = Addr.getOperand(0);
257        Offset = LoVal.getOperand(0);
258        return true;
259      }
260    }
261
262    // If an indexed load/store can be emitted, return false.
263    if (const LSBaseSDNode* LS = dyn_cast<LSBaseSDNode>(Parent))
264      if ((LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
265          Subtarget.hasMips32r2Or64())
266        return false;
267  }
268
269  Base   = Addr;
270  Offset = CurDAG->getTargetConstant(0, ValTy);
271  return true;
272}
273
274/// Select multiply instructions.
275std::pair<SDNode*, SDNode*>
276MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
277                             bool HasLo, bool HasHi) {
278  SDNode *Lo = 0, *Hi = 0;
279  SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
280                                       N->getOperand(1));
281  SDValue InFlag = SDValue(Mul, 0);
282
283  if (HasLo) {
284    Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
285                                Ty, MVT::Glue, InFlag);
286    InFlag = SDValue(Lo, 1);
287  }
288  if (HasHi)
289    Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
290                                Ty, InFlag);
291
292  return std::make_pair(Lo, Hi);
293}
294
295
296/// Select instructions not customized! Used for
297/// expanded, promoted and normal instructions
298SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
299  unsigned Opcode = Node->getOpcode();
300  DebugLoc dl = Node->getDebugLoc();
301
302  // Dump information about the Node being selected
303  DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
304
305  // If we have a custom node, we already have selected!
306  if (Node->isMachineOpcode()) {
307    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
308    return NULL;
309  }
310
311  ///
312  // Instruction Selection not handled by the auto-generated
313  // tablegen selection should be handled here.
314  ///
315  EVT NodeTy = Node->getValueType(0);
316  unsigned MultOpc;
317
318  switch(Opcode) {
319  default: break;
320
321  case ISD::SUBE:
322  case ISD::ADDE: {
323    SDValue InFlag = Node->getOperand(2), CmpLHS;
324    unsigned Opc = InFlag.getOpcode(); (void)Opc;
325    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
326            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
327           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
328
329    unsigned MOp;
330    if (Opcode == ISD::ADDE) {
331      CmpLHS = InFlag.getValue(0);
332      MOp = Mips::ADDu;
333    } else {
334      CmpLHS = InFlag.getOperand(0);
335      MOp = Mips::SUBu;
336    }
337
338    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
339
340    SDValue LHS = Node->getOperand(0);
341    SDValue RHS = Node->getOperand(1);
342
343    EVT VT = LHS.getValueType();
344    SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
345    SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
346                                              SDValue(Carry,0), RHS);
347
348    return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
349                                LHS, SDValue(AddCarry,0));
350  }
351
352  /// Mul with two results
353  case ISD::SMUL_LOHI:
354  case ISD::UMUL_LOHI: {
355    if (NodeTy == MVT::i32)
356      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
357    else
358      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
359
360    std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
361                                                  true, true);
362
363    if (!SDValue(Node, 0).use_empty())
364      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
365
366    if (!SDValue(Node, 1).use_empty())
367      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
368
369    return NULL;
370  }
371
372  /// Special Muls
373  case ISD::MUL: {
374    // Mips32 has a 32-bit three operand mul instruction.
375    if (Subtarget.hasMips32() && NodeTy == MVT::i32)
376      break;
377    return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
378                      dl, NodeTy, true, false).first;
379  }
380  case ISD::MULHS:
381  case ISD::MULHU: {
382    if (NodeTy == MVT::i32)
383      MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
384    else
385      MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
386
387    return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
388  }
389
390  // Get target GOT address.
391  case ISD::GLOBAL_OFFSET_TABLE:
392    return getGlobalBaseReg();
393
394  case ISD::ConstantFP: {
395    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
396    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
397      if (Subtarget.hasMips64()) {
398        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
399                                              Mips::ZERO_64, MVT::i64);
400        return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
401      }
402
403      SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
404                                            Mips::ZERO, MVT::i32);
405      return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
406                                    Zero);
407    }
408    break;
409  }
410
411  case ISD::Constant: {
412    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
413    unsigned Size = CN->getValueSizeInBits(0);
414
415    if (Size == 32)
416      break;
417
418    MipsAnalyzeImmediate AnalyzeImm;
419    int64_t Imm = CN->getSExtValue();
420
421    const MipsAnalyzeImmediate::InstSeq &Seq =
422      AnalyzeImm.Analyze(Imm, Size, false);
423
424    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
425    DebugLoc DL = CN->getDebugLoc();
426    SDNode *RegOpnd;
427    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
428                                                MVT::i64);
429
430    // The first instruction can be a LUi which is different from other
431    // instructions (ADDiu, ORI and SLL) in that it does not have a register
432    // operand.
433    if (Inst->Opc == Mips::LUi64)
434      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
435    else
436      RegOpnd =
437        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
438                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
439                               ImmOpnd);
440
441    // The remaining instructions in the sequence are handled here.
442    for (++Inst; Inst != Seq.end(); ++Inst) {
443      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
444                                          MVT::i64);
445      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
446                                       SDValue(RegOpnd, 0), ImmOpnd);
447    }
448
449    return RegOpnd;
450  }
451
452  case MipsISD::ThreadPointer: {
453    EVT PtrVT = TLI.getPointerTy();
454    unsigned RdhwrOpc, SrcReg, DestReg;
455
456    if (PtrVT == MVT::i32) {
457      RdhwrOpc = Mips::RDHWR;
458      SrcReg = Mips::HWR29;
459      DestReg = Mips::V1;
460    } else {
461      RdhwrOpc = Mips::RDHWR64;
462      SrcReg = Mips::HWR29_64;
463      DestReg = Mips::V1_64;
464    }
465
466    SDNode *Rdhwr =
467      CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
468                             Node->getValueType(0),
469                             CurDAG->getRegister(SrcReg, PtrVT));
470    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
471                                         SDValue(Rdhwr, 0));
472    SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
473    ReplaceUses(SDValue(Node, 0), ResNode);
474    return ResNode.getNode();
475  }
476  }
477
478  // Select the default instruction
479  SDNode *ResNode = SelectCode(Node);
480
481  DEBUG(errs() << "=> ");
482  if (ResNode == NULL || ResNode == Node)
483    DEBUG(Node->dump(CurDAG));
484  else
485    DEBUG(ResNode->dump(CurDAG));
486  DEBUG(errs() << "\n");
487  return ResNode;
488}
489
490bool MipsDAGToDAGISel::
491SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
492                             std::vector<SDValue> &OutOps) {
493  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
494  OutOps.push_back(Op);
495  return false;
496}
497
498/// createMipsISelDag - This pass converts a legalized DAG into a
499/// MIPS-specific DAG, ready for instruction scheduling.
500FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
501  return new MipsDAGToDAGISel(TM);
502}
503