PPCMCCodeEmitter.cpp revision 4f8dc7b17accf4f2ec953b80b2cc79786207492e 
1//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPCMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/PPCBaseInfo.h"
16#include "MCTargetDesc/PPCFixupKinds.h"
17#include "llvm/MC/MCCodeEmitter.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Support/ErrorHandling.h"
22using namespace llvm;
23
24STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
25
26namespace {
27class PPCMCCodeEmitter : public MCCodeEmitter {
28  PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
29  void operator=(const PPCMCCodeEmitter &);   // DO NOT IMPLEMENT
30
31public:
32  PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
33                   MCContext &ctx) {
34  }
35
36  ~PPCMCCodeEmitter() {}
37
38  unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
39                               SmallVectorImpl<MCFixup> &Fixups) const;
40  unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
41                             SmallVectorImpl<MCFixup> &Fixups) const;
42  unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
43                           SmallVectorImpl<MCFixup> &Fixups) const;
44  unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
45                           SmallVectorImpl<MCFixup> &Fixups) const;
46  unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
47                            SmallVectorImpl<MCFixup> &Fixups) const;
48  unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
49                             SmallVectorImpl<MCFixup> &Fixups) const;
50  unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
51                               SmallVectorImpl<MCFixup> &Fixups) const;
52
53  /// getMachineOpValue - Return binary encoding of operand. If the machine
54  /// operand requires relocation, record the relocation and return zero.
55  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
56                             SmallVectorImpl<MCFixup> &Fixups) const;
57
58  // getBinaryCodeForInstr - TableGen'erated function for getting the
59  // binary encoding for an instruction.
60  uint64_t getBinaryCodeForInstr(const MCInst &MI,
61                                 SmallVectorImpl<MCFixup> &Fixups) const;
62  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
63                         SmallVectorImpl<MCFixup> &Fixups) const {
64    unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
65
66    // Output the constant in big endian byte order.
67    for (unsigned i = 0; i != 4; ++i) {
68      OS << (char)(Bits >> 24);
69      Bits <<= 8;
70    }
71
72    ++MCNumEmitted;  // Keep track of the # of mi's emitted.
73  }
74
75};
76
77} // end anonymous namespace
78
79MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
80                                            const MCSubtargetInfo &STI,
81                                            MCContext &Ctx) {
82  return new PPCMCCodeEmitter(MCII, STI, Ctx);
83}
84
85unsigned PPCMCCodeEmitter::
86getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
87                    SmallVectorImpl<MCFixup> &Fixups) const {
88  const MCOperand &MO = MI.getOperand(OpNo);
89  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
90
91  // Add a fixup for the branch target.
92  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
93                                   (MCFixupKind)PPC::fixup_ppc_br24));
94  return 0;
95}
96
97unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
98                                     SmallVectorImpl<MCFixup> &Fixups) const {
99  const MCOperand &MO = MI.getOperand(OpNo);
100  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
101
102  // Add a fixup for the branch target.
103  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
104                                   (MCFixupKind)PPC::fixup_ppc_brcond14));
105  return 0;
106}
107
108unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
109                                       SmallVectorImpl<MCFixup> &Fixups) const {
110  const MCOperand &MO = MI.getOperand(OpNo);
111  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
112
113  // Add a fixup for the branch target.
114  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
115                                   (MCFixupKind)PPC::fixup_ppc_ha16));
116  return 0;
117}
118
119unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
120                                       SmallVectorImpl<MCFixup> &Fixups) const {
121  const MCOperand &MO = MI.getOperand(OpNo);
122  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
123
124  // Add a fixup for the branch target.
125  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
126                                   (MCFixupKind)PPC::fixup_ppc_lo16));
127  return 0;
128}
129
130unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
131                                            SmallVectorImpl<MCFixup> &Fixups) const {
132  // Encode (imm, reg) as a memri, which has the low 16-bits as the
133  // displacement and the next 5 bits as the register #.
134  assert(MI.getOperand(OpNo+1).isReg());
135  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
136
137  const MCOperand &MO = MI.getOperand(OpNo);
138  if (MO.isImm())
139    return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
140
141  // Add a fixup for the displacement field.
142  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
143                                   (MCFixupKind)PPC::fixup_ppc_lo16));
144  return RegBits;
145}
146
147
148unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
149                                       SmallVectorImpl<MCFixup> &Fixups) const {
150  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
151  // displacement and the next 5 bits as the register #.
152  assert(MI.getOperand(OpNo+1).isReg());
153  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
154
155  const MCOperand &MO = MI.getOperand(OpNo);
156  if (MO.isImm())
157    return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
158
159  // Add a fixup for the branch target.
160  Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
161                                   (MCFixupKind)PPC::fixup_ppc_lo14));
162  return RegBits;
163}
164
165
166unsigned PPCMCCodeEmitter::
167get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
168                    SmallVectorImpl<MCFixup> &Fixups) const {
169  const MCOperand &MO = MI.getOperand(OpNo);
170  assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
171         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
172  return 0x80 >> getPPCRegisterNumbering(MO.getReg());
173}
174
175
176unsigned PPCMCCodeEmitter::
177getMachineOpValue(const MCInst &MI, const MCOperand &MO,
178                  SmallVectorImpl<MCFixup> &Fixups) const {
179  if (MO.isReg()) {
180    // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
181    // The GPR operand should come through here though.
182    assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
183           MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
184    return getPPCRegisterNumbering(MO.getReg());
185  }
186
187  assert(MO.isImm() &&
188         "Relocation required in an instruction that we cannot encode!");
189  return MO.getImm();
190}
191
192
193#include "PPCGenMCCodeEmitter.inc"
194