X86MCInstLower.cpp revision c0115b5ca16af761199f17bf496403a5c7b710ec 
1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains code to lower X86 MachineInstrs to their corresponding
11// MCInst records.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86MCInstLower.h"
16#include "X86AsmPrinter.h"
17#include "X86COFFMachineModuleInfo.h"
18#include "X86MCAsmInfo.h"
19#include "llvm/CodeGen/MachineModuleInfoImpls.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCStreamer.h"
24#include "llvm/MC/MCSymbol.h"
25#include "llvm/Target/Mangler.h"
26#include "llvm/Support/FormattedStream.h"
27#include "llvm/ADT/SmallString.h"
28#include "llvm/Type.h"
29using namespace llvm;
30
31X86MCInstLower::X86MCInstLower(MCContext &ctx, Mangler *mang,
32                               X86AsmPrinter &asmprinter,
33                               const TargetMachine &tm)
34: Ctx(ctx), Mang(mang), AsmPrinter(asmprinter), MF(*AsmPrinter.MF),
35  TM(tm), MAI(*TM.getMCAsmInfo()) {}
36
37MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
38  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
39}
40
41
42MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
43  return static_cast<const X86TargetLowering*>(TM.getTargetLowering())->
44    getPICBaseSymbol(&MF, Ctx);
45}
46
47/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
48/// operand to an MCSymbol.
49MCSymbol *X86MCInstLower::
50GetSymbolFromOperand(const MachineOperand &MO) const {
51  assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
52
53  SmallString<128> Name;
54
55  if (!MO.isGlobal()) {
56    assert(MO.isSymbol());
57    Name += MAI.getGlobalPrefix();
58    Name += MO.getSymbolName();
59  } else {
60    const GlobalValue *GV = MO.getGlobal();
61    bool isImplicitlyPrivate = false;
62    if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
63        MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
64        MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
65        MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
66      isImplicitlyPrivate = true;
67
68    Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
69  }
70
71  // If the target flags on the operand changes the name of the symbol, do that
72  // before we return the symbol.
73  switch (MO.getTargetFlags()) {
74  default: break;
75  case X86II::MO_DLLIMPORT: {
76    // Handle dllimport linkage.
77    const char *Prefix = "__imp_";
78    Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
79    break;
80  }
81  case X86II::MO_DARWIN_NONLAZY:
82  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
83    Name += "$non_lazy_ptr";
84    MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
85
86    MachineModuleInfoImpl::StubValueTy &StubSym =
87      getMachOMMI().getGVStubEntry(Sym);
88    if (StubSym.getPointer() == 0) {
89      assert(MO.isGlobal() && "Extern symbol not handled yet");
90      StubSym =
91        MachineModuleInfoImpl::
92        StubValueTy(Mang->getSymbol(MO.getGlobal()),
93                    !MO.getGlobal()->hasInternalLinkage());
94    }
95    return Sym;
96  }
97  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
98    Name += "$non_lazy_ptr";
99    MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
100    MachineModuleInfoImpl::StubValueTy &StubSym =
101      getMachOMMI().getHiddenGVStubEntry(Sym);
102    if (StubSym.getPointer() == 0) {
103      assert(MO.isGlobal() && "Extern symbol not handled yet");
104      StubSym =
105        MachineModuleInfoImpl::
106        StubValueTy(Mang->getSymbol(MO.getGlobal()),
107                    !MO.getGlobal()->hasInternalLinkage());
108    }
109    return Sym;
110  }
111  case X86II::MO_DARWIN_STUB: {
112    Name += "$stub";
113    MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
114    MachineModuleInfoImpl::StubValueTy &StubSym =
115      getMachOMMI().getFnStubEntry(Sym);
116    if (StubSym.getPointer())
117      return Sym;
118
119    if (MO.isGlobal()) {
120      StubSym =
121        MachineModuleInfoImpl::
122        StubValueTy(Mang->getSymbol(MO.getGlobal()),
123                    !MO.getGlobal()->hasInternalLinkage());
124    } else {
125      Name.erase(Name.end()-5, Name.end());
126      StubSym =
127        MachineModuleInfoImpl::
128        StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
129    }
130    return Sym;
131  }
132  }
133
134  return Ctx.GetOrCreateSymbol(Name.str());
135}
136
137MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
138                                             MCSymbol *Sym) const {
139  // FIXME: We would like an efficient form for this, so we don't have to do a
140  // lot of extra uniquing.
141  const MCExpr *Expr = 0;
142  MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
143
144  switch (MO.getTargetFlags()) {
145  default: llvm_unreachable("Unknown target flag on GV operand");
146  case X86II::MO_NO_FLAG:    // No flag.
147  // These affect the name of the symbol, not any suffix.
148  case X86II::MO_DARWIN_NONLAZY:
149  case X86II::MO_DLLIMPORT:
150  case X86II::MO_DARWIN_STUB:
151    break;
152
153  case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
154  case X86II::MO_TLVP_PIC_BASE:
155    Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
156    // Subtract the pic base.
157    Expr = MCBinaryExpr::CreateSub(Expr,
158                                   MCSymbolRefExpr::Create(GetPICBaseSymbol(),
159                                                           Ctx),
160                                   Ctx);
161    break;
162  case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
163  case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
164  case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
165  case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
166  case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
167  case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
168  case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
169  case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
170  case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
171  case X86II::MO_PIC_BASE_OFFSET:
172  case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
173  case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
174    Expr = MCSymbolRefExpr::Create(Sym, Ctx);
175    // Subtract the pic base.
176    Expr = MCBinaryExpr::CreateSub(Expr,
177                               MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
178                                   Ctx);
179    if (MO.isJTI() && MAI.hasSetDirective()) {
180      // If .set directive is supported, use it to reduce the number of
181      // relocations the assembler will generate for differences between
182      // local labels. This is only safe when the symbols are in the same
183      // section so we are restricting it to jumptable references.
184      MCSymbol *Label = Ctx.CreateTempSymbol();
185      AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
186      Expr = MCSymbolRefExpr::Create(Label, Ctx);
187    }
188    break;
189  }
190
191  if (Expr == 0)
192    Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
193
194  if (!MO.isJTI() && MO.getOffset())
195    Expr = MCBinaryExpr::CreateAdd(Expr,
196                                   MCConstantExpr::Create(MO.getOffset(), Ctx),
197                                   Ctx);
198  return MCOperand::CreateExpr(Expr);
199}
200
201
202
203static void lower_subreg32(MCInst *MI, unsigned OpNo) {
204  // Convert registers in the addr mode according to subreg32.
205  unsigned Reg = MI->getOperand(OpNo).getReg();
206  if (Reg != 0)
207    MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
208}
209
210static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
211  // Convert registers in the addr mode according to subreg64.
212  for (unsigned i = 0; i != 4; ++i) {
213    if (!MI->getOperand(OpNo+i).isReg()) continue;
214
215    unsigned Reg = MI->getOperand(OpNo+i).getReg();
216    if (Reg == 0) continue;
217
218    MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
219  }
220}
221
222/// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
223static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
224  OutMI.setOpcode(NewOpc);
225  lower_subreg32(&OutMI, 0);
226}
227/// LowerUnaryToTwoAddr - R = setb   -> R = sbb R, R
228static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
229  OutMI.setOpcode(NewOpc);
230  OutMI.addOperand(OutMI.getOperand(0));
231  OutMI.addOperand(OutMI.getOperand(0));
232}
233
234/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
235/// a short fixed-register form.
236static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
237  unsigned ImmOp = Inst.getNumOperands() - 1;
238  assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
239         ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
240           Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
241          Inst.getNumOperands() == 2) && "Unexpected instruction!");
242
243  // Check whether the destination register can be fixed.
244  unsigned Reg = Inst.getOperand(0).getReg();
245  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
246    return;
247
248  // If so, rewrite the instruction.
249  MCOperand Saved = Inst.getOperand(ImmOp);
250  Inst = MCInst();
251  Inst.setOpcode(Opcode);
252  Inst.addOperand(Saved);
253}
254
255/// \brief Simplify things like MOV32rm to MOV32o32a.
256static void SimplifyShortMoveForm(MCInst &Inst, unsigned Opcode) {
257  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
258  unsigned AddrBase = IsStore;
259  unsigned RegOp = IsStore ? 0 : 5;
260  unsigned AddrOp = AddrBase + 3;
261  assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
262         Inst.getOperand(AddrBase + 0).isReg() && // base
263         Inst.getOperand(AddrBase + 1).isImm() && // scale
264         Inst.getOperand(AddrBase + 2).isReg() && // index register
265         (Inst.getOperand(AddrOp).isExpr() ||     // address
266          Inst.getOperand(AddrOp).isImm())&&
267         Inst.getOperand(AddrBase + 4).isReg() && // segment
268         "Unexpected instruction!");
269
270  // Check whether the destination register can be fixed.
271  unsigned Reg = Inst.getOperand(RegOp).getReg();
272  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
273    return;
274
275  // Check whether this is an absolute address.
276  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
277  // to do this here.
278  bool Absolute = true;
279  if (Inst.getOperand(AddrOp).isExpr()) {
280    const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
281    if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
282      if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
283        Absolute = false;
284  }
285
286  if (Absolute &&
287      (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
288       Inst.getOperand(AddrBase + 2).getReg() != 0 ||
289       Inst.getOperand(AddrBase + 4).getReg() != 0 ||
290       Inst.getOperand(AddrBase + 1).getImm() != 1))
291    return;
292
293  // If so, rewrite the instruction.
294  MCOperand Saved = Inst.getOperand(AddrOp);
295  Inst = MCInst();
296  Inst.setOpcode(Opcode);
297  Inst.addOperand(Saved);
298}
299
300void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
301  OutMI.setOpcode(MI->getOpcode());
302
303  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
304    const MachineOperand &MO = MI->getOperand(i);
305
306    MCOperand MCOp;
307    switch (MO.getType()) {
308    default:
309      MI->dump();
310      llvm_unreachable("unknown operand type");
311    case MachineOperand::MO_Register:
312      // Ignore all implicit register operands.
313      if (MO.isImplicit()) continue;
314      MCOp = MCOperand::CreateReg(MO.getReg());
315      break;
316    case MachineOperand::MO_Immediate:
317      MCOp = MCOperand::CreateImm(MO.getImm());
318      break;
319    case MachineOperand::MO_MachineBasicBlock:
320      MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
321                       MO.getMBB()->getSymbol(), Ctx));
322      break;
323    case MachineOperand::MO_GlobalAddress:
324      MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
325      break;
326    case MachineOperand::MO_ExternalSymbol:
327      MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
328      break;
329    case MachineOperand::MO_JumpTableIndex:
330      MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
331      break;
332    case MachineOperand::MO_ConstantPoolIndex:
333      MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
334      break;
335    case MachineOperand::MO_BlockAddress:
336      MCOp = LowerSymbolOperand(MO,
337                        AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
338      break;
339    }
340
341    OutMI.addOperand(MCOp);
342  }
343
344  // Handle a few special cases to eliminate operand modifiers.
345  switch (OutMI.getOpcode()) {
346  case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
347    lower_lea64_32mem(&OutMI, 1);
348    // FALL THROUGH.
349  case X86::LEA64r:
350  case X86::LEA16r:
351  case X86::LEA32r:
352    // LEA should have a segment register, but it must be empty.
353    assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
354           "Unexpected # of LEA operands");
355    assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
356           "LEA has segment specified!");
357    break;
358  case X86::MOVZX16rr8:   LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
359  case X86::MOVZX16rm8:   LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
360  case X86::MOVSX16rr8:   LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
361  case X86::MOVSX16rm8:   LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
362  case X86::MOVZX64rr32:  LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
363  case X86::MOVZX64rm32:  LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
364  case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
365  case X86::MOVZX64rr8:   LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
366  case X86::MOVZX64rm8:   LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
367  case X86::MOVZX64rr16:  LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
368  case X86::MOVZX64rm16:  LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
369  case X86::SETB_C8r:     LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
370  case X86::SETB_C16r:    LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
371  case X86::SETB_C32r:    LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
372  case X86::SETB_C64r:    LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
373  case X86::MOV8r0:       LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
374  case X86::MOV32r0:      LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
375  case X86::MMX_V_SET0:   LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
376  case X86::MMX_V_SETALLONES:
377    LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
378  case X86::FsFLD0SS:     LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
379  case X86::FsFLD0SD:     LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
380  case X86::V_SET0PS:     LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
381  case X86::V_SET0PD:     LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
382  case X86::V_SET0PI:     LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
383  case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
384
385  case X86::MOV16r0:
386    LowerSubReg32_Op0(OutMI, X86::MOV32r0);   // MOV16r0 -> MOV32r0
387    LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
388    break;
389  case X86::MOV64r0:
390    LowerSubReg32_Op0(OutMI, X86::MOV32r0);   // MOV64r0 -> MOV32r0
391    LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
392    break;
393
394  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have
395  // register inputs modeled as normal uses instead of implicit uses.  As such,
396  // truncate off all but the first operand (the callee).  FIXME: Change isel.
397  case X86::TAILJMPr64:
398  case X86::CALL64r:
399  case X86::CALL64pcrel32: {
400    unsigned Opcode = OutMI.getOpcode();
401    MCOperand Saved = OutMI.getOperand(0);
402    OutMI = MCInst();
403    OutMI.setOpcode(Opcode);
404    OutMI.addOperand(Saved);
405    break;
406  }
407
408  // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
409  case X86::TAILJMPr:
410  case X86::TAILJMPd:
411  case X86::TAILJMPd64: {
412    unsigned Opcode;
413    switch (OutMI.getOpcode()) {
414    default: assert(0 && "Invalid opcode");
415    case X86::TAILJMPr: Opcode = X86::JMP32r; break;
416    case X86::TAILJMPd:
417    case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
418    }
419
420    MCOperand Saved = OutMI.getOperand(0);
421    OutMI = MCInst();
422    OutMI.setOpcode(Opcode);
423    OutMI.addOperand(Saved);
424    break;
425  }
426
427  // The assembler backend wants to see branches in their small form and relax
428  // them to their large form.  The JIT can only handle the large form because
429  // it does not do relaxation.  For now, translate the large form to the
430  // small one here.
431  case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
432  case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
433  case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
434  case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
435  case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
436  case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
437  case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
438  case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
439  case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
440  case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
441  case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
442  case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
443  case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
444  case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
445  case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
446  case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
447  case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
448
449  // We don't currently select the correct instruction form for instructions
450  // which have a short %eax, etc. form. Handle this by custom lowering, for
451  // now.
452  //
453  // Note, we are currently not handling the following instructions:
454  // MOV64ao8, MOV64o8a
455  // XCHG16ar, XCHG32ar, XCHG64ar
456  case X86::MOV8mr_NOREX:
457  case X86::MOV8mr:     SimplifyShortMoveForm(OutMI, X86::MOV8ao8); break;
458  case X86::MOV8rm_NOREX:
459  case X86::MOV8rm:     SimplifyShortMoveForm(OutMI, X86::MOV8o8a); break;
460  case X86::MOV16mr:    SimplifyShortMoveForm(OutMI, X86::MOV16ao16); break;
461  case X86::MOV16rm:    SimplifyShortMoveForm(OutMI, X86::MOV16o16a); break;
462  case X86::MOV32mr:    SimplifyShortMoveForm(OutMI, X86::MOV32ao32); break;
463  case X86::MOV32rm:    SimplifyShortMoveForm(OutMI, X86::MOV32o32a); break;
464  case X86::MOV64mr:    SimplifyShortMoveForm(OutMI, X86::MOV64ao64); break;
465  case X86::MOV64rm:    SimplifyShortMoveForm(OutMI, X86::MOV64o64a); break;
466
467  case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
468  case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
469  case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
470  case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
471  case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
472  case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
473  case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
474  case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
475  case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
476  case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
477  case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
478  case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
479  case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
480  case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
481  case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
482  case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
483  case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
484  case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
485  case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
486  case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
487  case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
488  case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
489  case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
490  case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
491  case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
492  case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
493  case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
494  case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
495  case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
496  case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
497  case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
498  case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
499  case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
500  case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
501  case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
502  case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
503  }
504}
505
506
507void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
508  X86MCInstLower MCInstLowering(OutContext, Mang, *this, TM);
509  switch (MI->getOpcode()) {
510  case TargetOpcode::DBG_VALUE:
511    if (isVerbose() && OutStreamer.hasRawTextSupport()) {
512      std::string TmpStr;
513      raw_string_ostream OS(TmpStr);
514      PrintDebugValueComment(MI, OS);
515      OutStreamer.EmitRawText(StringRef(OS.str()));
516    }
517    return;
518
519  case X86::TAILJMPr:
520  case X86::TAILJMPd:
521  case X86::TAILJMPd64:
522    // Lower these as normal, but add some comments.
523    OutStreamer.AddComment("TAILCALL");
524    break;
525
526  case X86::MOVPC32r: {
527    MCInst TmpInst;
528    // This is a pseudo op for a two instruction sequence with a label, which
529    // looks like:
530    //     call "L1$pb"
531    // "L1$pb":
532    //     popl %esi
533
534    // Emit the call.
535    MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
536    TmpInst.setOpcode(X86::CALLpcrel32);
537    // FIXME: We would like an efficient form for this, so we don't have to do a
538    // lot of extra uniquing.
539    TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
540                                                                 OutContext)));
541    OutStreamer.EmitInstruction(TmpInst);
542
543    // Emit the label.
544    OutStreamer.EmitLabel(PICBase);
545
546    // popl $reg
547    TmpInst.setOpcode(X86::POP32r);
548    TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
549    OutStreamer.EmitInstruction(TmpInst);
550    return;
551  }
552
553  case X86::ADD32ri: {
554    // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
555    if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
556      break;
557
558    // Okay, we have something like:
559    //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
560
561    // For this, we want to print something like:
562    //   MYGLOBAL + (. - PICBASE)
563    // However, we can't generate a ".", so just emit a new label here and refer
564    // to it.
565    MCSymbol *DotSym = OutContext.CreateTempSymbol();
566    OutStreamer.EmitLabel(DotSym);
567
568    // Now that we have emitted the label, lower the complex operand expression.
569    MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
570
571    const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
572    const MCExpr *PICBase =
573      MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
574    DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
575
576    DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
577                                      DotExpr, OutContext);
578
579    MCInst TmpInst;
580    TmpInst.setOpcode(X86::ADD32ri);
581    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
582    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
583    TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
584    OutStreamer.EmitInstruction(TmpInst);
585    return;
586  }
587  }
588
589  MCInst TmpInst;
590  MCInstLowering.Lower(MI, TmpInst);
591  OutStreamer.EmitInstruction(TmpInst);
592}
593
594