AsmMatcherEmitter.cpp revision 3b5aec67ef174c74ff6620ddd71ad3b0cb39030c
1//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits a target specifier matcher for converting parsed 11// assembly operands in the MCInst structures. 12// 13// The input to the target specific matcher is a list of literal tokens and 14// operands. The target specific parser should generally eliminate any syntax 15// which is not relevant for matching; for example, comma tokens should have 16// already been consumed and eliminated by the parser. Most instructions will 17// end up with a single literal token (the instruction name) and some number of 18// operands. 19// 20// Some example inputs, for X86: 21// 'addl' (immediate ...) (register ...) 22// 'add' (immediate ...) (memory ...) 23// 'call' '*' %epc 24// 25// The assembly matcher is responsible for converting this input into a precise 26// machine instruction (i.e., an instruction with a well defined encoding). This 27// mapping has several properties which complicate matching: 28// 29// - It may be ambiguous; many architectures can legally encode particular 30// variants of an instruction in different ways (for example, using a smaller 31// encoding for small immediates). Such ambiguities should never be 32// arbitrarily resolved by the assembler, the assembler is always responsible 33// for choosing the "best" available instruction. 34// 35// - It may depend on the subtarget or the assembler context. Instructions 36// which are invalid for the current mode, but otherwise unambiguous (e.g., 37// an SSE instruction in a file being assembled for i486) should be accepted 38// and rejected by the assembler front end. However, if the proper encoding 39// for an instruction is dependent on the assembler context then the matcher 40// is responsible for selecting the correct machine instruction for the 41// current mode. 42// 43// The core matching algorithm attempts to exploit the regularity in most 44// instruction sets to quickly determine the set of possibly matching 45// instructions, and the simplify the generated code. Additionally, this helps 46// to ensure that the ambiguities are intentionally resolved by the user. 47// 48// The matching is divided into two distinct phases: 49// 50// 1. Classification: Each operand is mapped to the unique set which (a) 51// contains it, and (b) is the largest such subset for which a single 52// instruction could match all members. 53// 54// For register classes, we can generate these subgroups automatically. For 55// arbitrary operands, we expect the user to define the classes and their 56// relations to one another (for example, 8-bit signed immediates as a 57// subset of 32-bit immediates). 58// 59// By partitioning the operands in this way, we guarantee that for any 60// tuple of classes, any single instruction must match either all or none 61// of the sets of operands which could classify to that tuple. 62// 63// In addition, the subset relation amongst classes induces a partial order 64// on such tuples, which we use to resolve ambiguities. 65// 66// FIXME: What do we do if a crazy case shows up where this is the wrong 67// resolution? 68// 69// 2. The input can now be treated as a tuple of classes (static tokens are 70// simple singleton sets). Each such tuple should generally map to a single 71// instruction (we currently ignore cases where this isn't true, whee!!!), 72// which we can emit a simple matcher for. 73// 74//===----------------------------------------------------------------------===// 75 76#include "AsmMatcherEmitter.h" 77#include "CodeGenTarget.h" 78#include "Record.h" 79#include "StringMatcher.h" 80#include "llvm/ADT/OwningPtr.h" 81#include "llvm/ADT/SmallPtrSet.h" 82#include "llvm/ADT/SmallVector.h" 83#include "llvm/ADT/STLExtras.h" 84#include "llvm/ADT/StringExtras.h" 85#include "llvm/Support/CommandLine.h" 86#include "llvm/Support/Debug.h" 87#include <list> 88#include <map> 89#include <set> 90using namespace llvm; 91 92static cl::opt<std::string> 93MatchPrefix("match-prefix", cl::init(""), 94 cl::desc("Only match instructions with the given prefix")); 95 96 97namespace { 98 class AsmMatcherInfo; 99struct SubtargetFeatureInfo; 100 101/// ClassInfo - Helper class for storing the information about a particular 102/// class of operands which can be matched. 103struct ClassInfo { 104 enum ClassInfoKind { 105 /// Invalid kind, for use as a sentinel value. 106 Invalid = 0, 107 108 /// The class for a particular token. 109 Token, 110 111 /// The (first) register class, subsequent register classes are 112 /// RegisterClass0+1, and so on. 113 RegisterClass0, 114 115 /// The (first) user defined class, subsequent user defined classes are 116 /// UserClass0+1, and so on. 117 UserClass0 = 1<<16 118 }; 119 120 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 + 121 /// N) for the Nth user defined class. 122 unsigned Kind; 123 124 /// SuperClasses - The super classes of this class. Note that for simplicities 125 /// sake user operands only record their immediate super class, while register 126 /// operands include all superclasses. 127 std::vector<ClassInfo*> SuperClasses; 128 129 /// Name - The full class name, suitable for use in an enum. 130 std::string Name; 131 132 /// ClassName - The unadorned generic name for this class (e.g., Token). 133 std::string ClassName; 134 135 /// ValueName - The name of the value this class represents; for a token this 136 /// is the literal token string, for an operand it is the TableGen class (or 137 /// empty if this is a derived class). 138 std::string ValueName; 139 140 /// PredicateMethod - The name of the operand method to test whether the 141 /// operand matches this class; this is not valid for Token or register kinds. 142 std::string PredicateMethod; 143 144 /// RenderMethod - The name of the operand method to add this operand to an 145 /// MCInst; this is not valid for Token or register kinds. 146 std::string RenderMethod; 147 148 /// For register classes, the records for all the registers in this class. 149 std::set<Record*> Registers; 150 151public: 152 /// isRegisterClass() - Check if this is a register class. 153 bool isRegisterClass() const { 154 return Kind >= RegisterClass0 && Kind < UserClass0; 155 } 156 157 /// isUserClass() - Check if this is a user defined class. 158 bool isUserClass() const { 159 return Kind >= UserClass0; 160 } 161 162 /// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes 163 /// are related if they are in the same class hierarchy. 164 bool isRelatedTo(const ClassInfo &RHS) const { 165 // Tokens are only related to tokens. 166 if (Kind == Token || RHS.Kind == Token) 167 return Kind == Token && RHS.Kind == Token; 168 169 // Registers classes are only related to registers classes, and only if 170 // their intersection is non-empty. 171 if (isRegisterClass() || RHS.isRegisterClass()) { 172 if (!isRegisterClass() || !RHS.isRegisterClass()) 173 return false; 174 175 std::set<Record*> Tmp; 176 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin()); 177 std::set_intersection(Registers.begin(), Registers.end(), 178 RHS.Registers.begin(), RHS.Registers.end(), 179 II); 180 181 return !Tmp.empty(); 182 } 183 184 // Otherwise we have two users operands; they are related if they are in the 185 // same class hierarchy. 186 // 187 // FIXME: This is an oversimplification, they should only be related if they 188 // intersect, however we don't have that information. 189 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!"); 190 const ClassInfo *Root = this; 191 while (!Root->SuperClasses.empty()) 192 Root = Root->SuperClasses.front(); 193 194 const ClassInfo *RHSRoot = &RHS; 195 while (!RHSRoot->SuperClasses.empty()) 196 RHSRoot = RHSRoot->SuperClasses.front(); 197 198 return Root == RHSRoot; 199 } 200 201 /// isSubsetOf - Test whether this class is a subset of \arg RHS; 202 bool isSubsetOf(const ClassInfo &RHS) const { 203 // This is a subset of RHS if it is the same class... 204 if (this == &RHS) 205 return true; 206 207 // ... or if any of its super classes are a subset of RHS. 208 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(), 209 ie = SuperClasses.end(); it != ie; ++it) 210 if ((*it)->isSubsetOf(RHS)) 211 return true; 212 213 return false; 214 } 215 216 /// operator< - Compare two classes. 217 bool operator<(const ClassInfo &RHS) const { 218 if (this == &RHS) 219 return false; 220 221 // Unrelated classes can be ordered by kind. 222 if (!isRelatedTo(RHS)) 223 return Kind < RHS.Kind; 224 225 switch (Kind) { 226 case Invalid: 227 assert(0 && "Invalid kind!"); 228 case Token: 229 // Tokens are comparable by value. 230 // 231 // FIXME: Compare by enum value. 232 return ValueName < RHS.ValueName; 233 234 default: 235 // This class preceeds the RHS if it is a proper subset of the RHS. 236 if (isSubsetOf(RHS)) 237 return true; 238 if (RHS.isSubsetOf(*this)) 239 return false; 240 241 // Otherwise, order by name to ensure we have a total ordering. 242 return ValueName < RHS.ValueName; 243 } 244 } 245}; 246 247/// MatchableInfo - Helper class for storing the necessary information for an 248/// instruction or alias which is capable of being matched. 249struct MatchableInfo { 250 struct Operand { 251 /// Token - This is the token that the operand came from. 252 StringRef Token; 253 254 /// The unique class instance this operand should match. 255 ClassInfo *Class; 256 257 /// The original operand this corresponds to, if any. 258 const CGIOperandList::OperandInfo *OperandInfo; 259 260 explicit Operand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} 261 }; 262 263 /// InstrName - The target name for this instruction. 264 std::string InstrName; 265 266 /// TheDef - This is the definition of the instruction or InstAlias that this 267 /// matchable came from. 268 Record *const TheDef; 269 270 /// OperandList - This is the operand list that came from the (ins) and (outs) 271 /// list of the alias or instruction. 272 const CGIOperandList &OperandList; 273 274 /// AsmString - The assembly string for this instruction (with variants 275 /// removed), e.g. "movsx $src, $dst". 276 std::string AsmString; 277 278 /// Mnemonic - This is the first token of the matched instruction, its 279 /// mnemonic. 280 StringRef Mnemonic; 281 282 /// AsmOperands - The textual operands that this instruction matches, 283 /// annotated with a class and where in the OperandList they were defined. 284 /// This directly corresponds to the tokenized AsmString after the mnemonic is 285 /// removed. 286 SmallVector<Operand, 4> AsmOperands; 287 288 /// Predicates - The required subtarget features to match this instruction. 289 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures; 290 291 /// ConversionFnKind - The enum value which is passed to the generated 292 /// ConvertToMCInst to convert parsed operands into an MCInst for this 293 /// function. 294 std::string ConversionFnKind; 295 296 MatchableInfo(const CodeGenInstruction &CGI) 297 : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) { 298 InstrName = TheDef->getName(); 299 } 300 301 MatchableInfo(const CodeGenInstAlias *Alias) 302 : TheDef(Alias->TheDef), OperandList(Alias->Operands), 303 AsmString(Alias->AsmString) { 304 305 // FIXME: Huge hack. 306 DefInit *DI = dynamic_cast<DefInit*>(Alias->Result->getOperator()); 307 assert(DI); 308 309 InstrName = DI->getDef()->getName(); 310 } 311 312 void Initialize(const AsmMatcherInfo &Info, 313 SmallPtrSet<Record*, 16> &SingletonRegisters); 314 315 /// Validate - Return true if this matchable is a valid thing to match against 316 /// and perform a bunch of validity checking. 317 bool Validate(StringRef CommentDelimiter, bool Hack) const; 318 319 /// getSingletonRegisterForAsmOperand - If the specified token is a singleton 320 /// register, return the Record for it, otherwise return null. 321 Record *getSingletonRegisterForAsmOperand(unsigned i, 322 const AsmMatcherInfo &Info) const; 323 324 /// operator< - Compare two matchables. 325 bool operator<(const MatchableInfo &RHS) const { 326 // The primary comparator is the instruction mnemonic. 327 if (Mnemonic != RHS.Mnemonic) 328 return Mnemonic < RHS.Mnemonic; 329 330 if (AsmOperands.size() != RHS.AsmOperands.size()) 331 return AsmOperands.size() < RHS.AsmOperands.size(); 332 333 // Compare lexicographically by operand. The matcher validates that other 334 // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith(). 335 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 336 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 337 return true; 338 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 339 return false; 340 } 341 342 return false; 343 } 344 345 /// CouldMatchAmiguouslyWith - Check whether this matchable could 346 /// ambiguously match the same set of operands as \arg RHS (without being a 347 /// strictly superior match). 348 bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) { 349 // The primary comparator is the instruction mnemonic. 350 if (Mnemonic != RHS.Mnemonic) 351 return false; 352 353 // The number of operands is unambiguous. 354 if (AsmOperands.size() != RHS.AsmOperands.size()) 355 return false; 356 357 // Otherwise, make sure the ordering of the two instructions is unambiguous 358 // by checking that either (a) a token or operand kind discriminates them, 359 // or (b) the ordering among equivalent kinds is consistent. 360 361 // Tokens and operand kinds are unambiguous (assuming a correct target 362 // specific parser). 363 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 364 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind || 365 AsmOperands[i].Class->Kind == ClassInfo::Token) 366 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class || 367 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 368 return false; 369 370 // Otherwise, this operand could commute if all operands are equivalent, or 371 // there is a pair of operands that compare less than and a pair that 372 // compare greater than. 373 bool HasLT = false, HasGT = false; 374 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 375 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 376 HasLT = true; 377 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 378 HasGT = true; 379 } 380 381 return !(HasLT ^ HasGT); 382 } 383 384 void dump(); 385 386private: 387 void TokenizeAsmString(const AsmMatcherInfo &Info); 388}; 389 390/// SubtargetFeatureInfo - Helper class for storing information on a subtarget 391/// feature which participates in instruction matching. 392struct SubtargetFeatureInfo { 393 /// \brief The predicate record for this feature. 394 Record *TheDef; 395 396 /// \brief An unique index assigned to represent this feature. 397 unsigned Index; 398 399 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} 400 401 /// \brief The name of the enumerated constant identifying this feature. 402 std::string getEnumName() const { 403 return "Feature_" + TheDef->getName(); 404 } 405}; 406 407class AsmMatcherInfo { 408public: 409 /// The tablegen AsmParser record. 410 Record *AsmParser; 411 412 /// Target - The target information. 413 CodeGenTarget &Target; 414 415 /// The AsmParser "RegisterPrefix" value. 416 std::string RegisterPrefix; 417 418 /// The classes which are needed for matching. 419 std::vector<ClassInfo*> Classes; 420 421 /// The information on the matchables to match. 422 std::vector<MatchableInfo*> Matchables; 423 424 /// Map of Register records to their class information. 425 std::map<Record*, ClassInfo*> RegisterClasses; 426 427 /// Map of Predicate records to their subtarget information. 428 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures; 429 430private: 431 /// Map of token to class information which has already been constructed. 432 std::map<std::string, ClassInfo*> TokenClasses; 433 434 /// Map of RegisterClass records to their class information. 435 std::map<Record*, ClassInfo*> RegisterClassClasses; 436 437 /// Map of AsmOperandClass records to their class information. 438 std::map<Record*, ClassInfo*> AsmOperandClasses; 439 440private: 441 /// getTokenClass - Lookup or create the class for the given token. 442 ClassInfo *getTokenClass(StringRef Token); 443 444 /// getOperandClass - Lookup or create the class for the given operand. 445 ClassInfo *getOperandClass(StringRef Token, 446 const CGIOperandList::OperandInfo &OI); 447 448 /// BuildRegisterClasses - Build the ClassInfo* instances for register 449 /// classes. 450 void BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters); 451 452 /// BuildOperandClasses - Build the ClassInfo* instances for user defined 453 /// operand classes. 454 void BuildOperandClasses(); 455 456public: 457 AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target); 458 459 /// BuildInfo - Construct the various tables used during matching. 460 void BuildInfo(); 461 462 /// getSubtargetFeature - Lookup or create the subtarget feature info for the 463 /// given operand. 464 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { 465 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); 466 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I = 467 SubtargetFeatures.find(Def); 468 return I == SubtargetFeatures.end() ? 0 : I->second; 469 } 470}; 471 472} 473 474void MatchableInfo::dump() { 475 errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n"; 476 477 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 478 Operand &Op = AsmOperands[i]; 479 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; 480 if (Op.Class->Kind == ClassInfo::Token) { 481 errs() << '\"' << Op.Token << "\"\n"; 482 continue; 483 } 484 485 if (!Op.OperandInfo) { 486 errs() << "(singleton register)\n"; 487 continue; 488 } 489 490 const CGIOperandList::OperandInfo &OI = *Op.OperandInfo; 491 errs() << OI.Name << " " << OI.Rec->getName() 492 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n"; 493 } 494} 495 496void MatchableInfo::Initialize(const AsmMatcherInfo &Info, 497 SmallPtrSet<Record*, 16> &SingletonRegisters) { 498 // TODO: Eventually support asmparser for Variant != 0. 499 AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); 500 501 TokenizeAsmString(Info); 502 503 // Compute the require features. 504 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates"); 505 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) 506 if (SubtargetFeatureInfo *Feature = 507 Info.getSubtargetFeature(Predicates[i])) 508 RequiredFeatures.push_back(Feature); 509 510 // Collect singleton registers, if used. 511 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 512 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info)) 513 SingletonRegisters.insert(Reg); 514 } 515} 516 517/// TokenizeAsmString - Tokenize a simplified assembly string. 518void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { 519 StringRef String = AsmString; 520 unsigned Prev = 0; 521 bool InTok = true; 522 for (unsigned i = 0, e = String.size(); i != e; ++i) { 523 switch (String[i]) { 524 case '[': 525 case ']': 526 case '*': 527 case '!': 528 case ' ': 529 case '\t': 530 case ',': 531 if (InTok) { 532 AsmOperands.push_back(Operand(String.slice(Prev, i))); 533 InTok = false; 534 } 535 if (!isspace(String[i]) && String[i] != ',') 536 AsmOperands.push_back(Operand(String.substr(i, 1))); 537 Prev = i + 1; 538 break; 539 540 case '\\': 541 if (InTok) { 542 AsmOperands.push_back(Operand(String.slice(Prev, i))); 543 InTok = false; 544 } 545 ++i; 546 assert(i != String.size() && "Invalid quoted character"); 547 AsmOperands.push_back(Operand(String.substr(i, 1))); 548 Prev = i + 1; 549 break; 550 551 case '$': { 552 // If this isn't "${", treat like a normal token. 553 if (i + 1 == String.size() || String[i + 1] != '{') { 554 if (InTok) { 555 AsmOperands.push_back(Operand(String.slice(Prev, i))); 556 InTok = false; 557 } 558 Prev = i; 559 break; 560 } 561 562 if (InTok) { 563 AsmOperands.push_back(Operand(String.slice(Prev, i))); 564 InTok = false; 565 } 566 567 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); 568 assert(End != String.end() && "Missing brace in operand reference!"); 569 size_t EndPos = End - String.begin(); 570 AsmOperands.push_back(Operand(String.slice(i, EndPos+1))); 571 Prev = EndPos + 1; 572 i = EndPos; 573 break; 574 } 575 576 case '.': 577 if (InTok) 578 AsmOperands.push_back(Operand(String.slice(Prev, i))); 579 Prev = i; 580 InTok = true; 581 break; 582 583 default: 584 InTok = true; 585 } 586 } 587 if (InTok && Prev != String.size()) 588 AsmOperands.push_back(Operand(String.substr(Prev))); 589 590 // The first token of the instruction is the mnemonic, which must be a 591 // simple string, not a $foo variable or a singleton register. 592 assert(!AsmOperands.empty() && "Instruction has no tokens?"); 593 Mnemonic = AsmOperands[0].Token; 594 if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info)) 595 throw TGError(TheDef->getLoc(), 596 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); 597 598 // Remove the first operand, it is tracked in the mnemonic field. 599 AsmOperands.erase(AsmOperands.begin()); 600} 601 602 603 604/// getRegisterRecord - Get the register record for \arg name, or 0. 605static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) { 606 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { 607 const CodeGenRegister &Reg = Target.getRegisters()[i]; 608 if (Name == Reg.TheDef->getValueAsString("AsmName")) 609 return Reg.TheDef; 610 } 611 612 return 0; 613} 614 615bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { 616 // Reject matchables with no .s string. 617 if (AsmString.empty()) 618 throw TGError(TheDef->getLoc(), "instruction with empty asm string"); 619 620 // Reject any matchables with a newline in them, they should be marked 621 // isCodeGenOnly if they are pseudo instructions. 622 if (AsmString.find('\n') != std::string::npos) 623 throw TGError(TheDef->getLoc(), 624 "multiline instruction is not valid for the asmparser, " 625 "mark it isCodeGenOnly"); 626 627 // Remove comments from the asm string. We know that the asmstring only 628 // has one line. 629 if (!CommentDelimiter.empty() && 630 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos) 631 throw TGError(TheDef->getLoc(), 632 "asmstring for instruction has comment character in it, " 633 "mark it isCodeGenOnly"); 634 635 // Reject matchables with operand modifiers, these aren't something we can 636 /// handle, the target should be refactored to use operands instead of 637 /// modifiers. 638 // 639 // Also, check for instructions which reference the operand multiple times; 640 // this implies a constraint we would not honor. 641 std::set<std::string> OperandNames; 642 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 643 StringRef Tok = AsmOperands[i].Token; 644 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos) 645 throw TGError(TheDef->getLoc(), 646 "matchable with operand modifier '" + Tok.str() + 647 "' not supported by asm matcher. Mark isCodeGenOnly!"); 648 649 // Verify that any operand is only mentioned once. 650 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { 651 if (!Hack) 652 throw TGError(TheDef->getLoc(), 653 "ERROR: matchable with tied operand '" + Tok.str() + 654 "' can never be matched!"); 655 // FIXME: Should reject these. The ARM backend hits this with $lane in a 656 // bunch of instructions. It is unclear what the right answer is. 657 DEBUG({ 658 errs() << "warning: '" << InstrName << "': " 659 << "ignoring instruction with tied operand '" 660 << Tok.str() << "'\n"; 661 }); 662 return false; 663 } 664 } 665 666 return true; 667} 668 669 670/// getSingletonRegisterForAsmOperand - If the specified token is a singleton 671/// register, return the register name, otherwise return a null StringRef. 672Record *MatchableInfo:: 673getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ 674 StringRef Tok = AsmOperands[i].Token; 675 if (!Tok.startswith(Info.RegisterPrefix)) 676 return 0; 677 678 StringRef RegName = Tok.substr(Info.RegisterPrefix.size()); 679 if (Record *Rec = getRegisterRecord(Info.Target, RegName)) 680 return Rec; 681 682 // If there is no register prefix (i.e. "%" in "%eax"), then this may 683 // be some random non-register token, just ignore it. 684 if (Info.RegisterPrefix.empty()) 685 return 0; 686 687 std::string Err = "unable to find register for '" + RegName.str() + 688 "' (which matches register prefix)"; 689 throw TGError(TheDef->getLoc(), Err); 690} 691 692 693static std::string getEnumNameForToken(StringRef Str) { 694 std::string Res; 695 696 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) { 697 switch (*it) { 698 case '*': Res += "_STAR_"; break; 699 case '%': Res += "_PCT_"; break; 700 case ':': Res += "_COLON_"; break; 701 default: 702 if (isalnum(*it)) 703 Res += *it; 704 else 705 Res += "_" + utostr((unsigned) *it) + "_"; 706 } 707 } 708 709 return Res; 710} 711 712ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { 713 ClassInfo *&Entry = TokenClasses[Token]; 714 715 if (!Entry) { 716 Entry = new ClassInfo(); 717 Entry->Kind = ClassInfo::Token; 718 Entry->ClassName = "Token"; 719 Entry->Name = "MCK_" + getEnumNameForToken(Token); 720 Entry->ValueName = Token; 721 Entry->PredicateMethod = "<invalid>"; 722 Entry->RenderMethod = "<invalid>"; 723 Classes.push_back(Entry); 724 } 725 726 return Entry; 727} 728 729ClassInfo * 730AsmMatcherInfo::getOperandClass(StringRef Token, 731 const CGIOperandList::OperandInfo &OI) { 732 if (OI.Rec->isSubClassOf("RegisterClass")) { 733 ClassInfo *CI = RegisterClassClasses[OI.Rec]; 734 735 if (!CI) 736 throw TGError(OI.Rec->getLoc(), "register class has no class info!"); 737 738 return CI; 739 } 740 741 assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!"); 742 Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass"); 743 ClassInfo *CI = AsmOperandClasses[MatchClass]; 744 745 if (!CI) 746 throw TGError(OI.Rec->getLoc(), "operand has no match class!"); 747 748 return CI; 749} 750 751void AsmMatcherInfo:: 752BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { 753 std::vector<CodeGenRegisterClass> RegisterClasses; 754 std::vector<CodeGenRegister> Registers; 755 756 RegisterClasses = Target.getRegisterClasses(); 757 Registers = Target.getRegisters(); 758 759 // The register sets used for matching. 760 std::set< std::set<Record*> > RegisterSets; 761 762 // Gather the defined sets. 763 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(), 764 ie = RegisterClasses.end(); it != ie; ++it) 765 RegisterSets.insert(std::set<Record*>(it->Elements.begin(), 766 it->Elements.end())); 767 768 // Add any required singleton sets. 769 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 770 ie = SingletonRegisters.end(); it != ie; ++it) { 771 Record *Rec = *it; 772 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1)); 773 } 774 775 // Introduce derived sets where necessary (when a register does not determine 776 // a unique register set class), and build the mapping of registers to the set 777 // they should classify to. 778 std::map<Record*, std::set<Record*> > RegisterMap; 779 for (std::vector<CodeGenRegister>::iterator it = Registers.begin(), 780 ie = Registers.end(); it != ie; ++it) { 781 CodeGenRegister &CGR = *it; 782 // Compute the intersection of all sets containing this register. 783 std::set<Record*> ContainingSet; 784 785 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 786 ie = RegisterSets.end(); it != ie; ++it) { 787 if (!it->count(CGR.TheDef)) 788 continue; 789 790 if (ContainingSet.empty()) { 791 ContainingSet = *it; 792 } else { 793 std::set<Record*> Tmp; 794 std::swap(Tmp, ContainingSet); 795 std::insert_iterator< std::set<Record*> > II(ContainingSet, 796 ContainingSet.begin()); 797 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), 798 II); 799 } 800 } 801 802 if (!ContainingSet.empty()) { 803 RegisterSets.insert(ContainingSet); 804 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet)); 805 } 806 } 807 808 // Construct the register classes. 809 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses; 810 unsigned Index = 0; 811 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 812 ie = RegisterSets.end(); it != ie; ++it, ++Index) { 813 ClassInfo *CI = new ClassInfo(); 814 CI->Kind = ClassInfo::RegisterClass0 + Index; 815 CI->ClassName = "Reg" + utostr(Index); 816 CI->Name = "MCK_Reg" + utostr(Index); 817 CI->ValueName = ""; 818 CI->PredicateMethod = ""; // unused 819 CI->RenderMethod = "addRegOperands"; 820 CI->Registers = *it; 821 Classes.push_back(CI); 822 RegisterSetClasses.insert(std::make_pair(*it, CI)); 823 } 824 825 // Find the superclasses; we could compute only the subgroup lattice edges, 826 // but there isn't really a point. 827 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 828 ie = RegisterSets.end(); it != ie; ++it) { 829 ClassInfo *CI = RegisterSetClasses[*it]; 830 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(), 831 ie2 = RegisterSets.end(); it2 != ie2; ++it2) 832 if (*it != *it2 && 833 std::includes(it2->begin(), it2->end(), it->begin(), it->end())) 834 CI->SuperClasses.push_back(RegisterSetClasses[*it2]); 835 } 836 837 // Name the register classes which correspond to a user defined RegisterClass. 838 for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(), 839 ie = RegisterClasses.end(); it != ie; ++it) { 840 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(), 841 it->Elements.end())]; 842 if (CI->ValueName.empty()) { 843 CI->ClassName = it->getName(); 844 CI->Name = "MCK_" + it->getName(); 845 CI->ValueName = it->getName(); 846 } else 847 CI->ValueName = CI->ValueName + "," + it->getName(); 848 849 RegisterClassClasses.insert(std::make_pair(it->TheDef, CI)); 850 } 851 852 // Populate the map for individual registers. 853 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(), 854 ie = RegisterMap.end(); it != ie; ++it) 855 this->RegisterClasses[it->first] = RegisterSetClasses[it->second]; 856 857 // Name the register classes which correspond to singleton registers. 858 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 859 ie = SingletonRegisters.end(); it != ie; ++it) { 860 Record *Rec = *it; 861 ClassInfo *CI = this->RegisterClasses[Rec]; 862 assert(CI && "Missing singleton register class info!"); 863 864 if (CI->ValueName.empty()) { 865 CI->ClassName = Rec->getName(); 866 CI->Name = "MCK_" + Rec->getName(); 867 CI->ValueName = Rec->getName(); 868 } else 869 CI->ValueName = CI->ValueName + "," + Rec->getName(); 870 } 871} 872 873void AsmMatcherInfo::BuildOperandClasses() { 874 std::vector<Record*> AsmOperands = 875 Records.getAllDerivedDefinitions("AsmOperandClass"); 876 877 // Pre-populate AsmOperandClasses map. 878 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 879 ie = AsmOperands.end(); it != ie; ++it) 880 AsmOperandClasses[*it] = new ClassInfo(); 881 882 unsigned Index = 0; 883 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 884 ie = AsmOperands.end(); it != ie; ++it, ++Index) { 885 ClassInfo *CI = AsmOperandClasses[*it]; 886 CI->Kind = ClassInfo::UserClass0 + Index; 887 888 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses"); 889 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) { 890 DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i)); 891 if (!DI) { 892 PrintError((*it)->getLoc(), "Invalid super class reference!"); 893 continue; 894 } 895 896 ClassInfo *SC = AsmOperandClasses[DI->getDef()]; 897 if (!SC) 898 PrintError((*it)->getLoc(), "Invalid super class reference!"); 899 else 900 CI->SuperClasses.push_back(SC); 901 } 902 CI->ClassName = (*it)->getValueAsString("Name"); 903 CI->Name = "MCK_" + CI->ClassName; 904 CI->ValueName = (*it)->getName(); 905 906 // Get or construct the predicate method name. 907 Init *PMName = (*it)->getValueInit("PredicateMethod"); 908 if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) { 909 CI->PredicateMethod = SI->getValue(); 910 } else { 911 assert(dynamic_cast<UnsetInit*>(PMName) && 912 "Unexpected PredicateMethod field!"); 913 CI->PredicateMethod = "is" + CI->ClassName; 914 } 915 916 // Get or construct the render method name. 917 Init *RMName = (*it)->getValueInit("RenderMethod"); 918 if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) { 919 CI->RenderMethod = SI->getValue(); 920 } else { 921 assert(dynamic_cast<UnsetInit*>(RMName) && 922 "Unexpected RenderMethod field!"); 923 CI->RenderMethod = "add" + CI->ClassName + "Operands"; 924 } 925 926 AsmOperandClasses[*it] = CI; 927 Classes.push_back(CI); 928 } 929} 930 931AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target) 932 : AsmParser(asmParser), Target(target), 933 RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { 934} 935 936 937void AsmMatcherInfo::BuildInfo() { 938 // Build information about all of the AssemblerPredicates. 939 std::vector<Record*> AllPredicates = 940 Records.getAllDerivedDefinitions("Predicate"); 941 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) { 942 Record *Pred = AllPredicates[i]; 943 // Ignore predicates that are not intended for the assembler. 944 if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) 945 continue; 946 947 if (Pred->getName().empty()) 948 throw TGError(Pred->getLoc(), "Predicate has no name!"); 949 950 unsigned FeatureNo = SubtargetFeatures.size(); 951 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); 952 assert(FeatureNo < 32 && "Too many subtarget features!"); 953 } 954 955 StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); 956 957 // Parse the instructions; we need to do this first so that we can gather the 958 // singleton register classes. 959 SmallPtrSet<Record*, 16> SingletonRegisters; 960 for (CodeGenTarget::inst_iterator I = Target.inst_begin(), 961 E = Target.inst_end(); I != E; ++I) { 962 const CodeGenInstruction &CGI = **I; 963 964 // If the tblgen -match-prefix option is specified (for tblgen hackers), 965 // filter the set of instructions we consider. 966 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix)) 967 continue; 968 969 // Ignore "codegen only" instructions. 970 if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) 971 continue; 972 973 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI)); 974 975 II->Initialize(*this, SingletonRegisters); 976 977 // Ignore instructions which shouldn't be matched and diagnose invalid 978 // instruction definitions with an error. 979 if (!II->Validate(CommentDelimiter, true)) 980 continue; 981 982 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. 983 // 984 // FIXME: This is a total hack. 985 if (StringRef(II->InstrName).startswith("Int_") || 986 StringRef(II->InstrName).endswith("_Int")) 987 continue; 988 989 Matchables.push_back(II.take()); 990 } 991 992 // Parse all of the InstAlias definitions and stick them in the list of 993 // matchables. 994 std::vector<Record*> AllInstAliases = 995 Records.getAllDerivedDefinitions("InstAlias"); 996 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { 997 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]); 998 999 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias)); 1000 1001 II->Initialize(*this, SingletonRegisters); 1002 1003 // Validate the alias definitions. 1004 II->Validate(CommentDelimiter, false); 1005 1006 Matchables.push_back(II.take()); 1007 } 1008 1009 // Build info for the register classes. 1010 BuildRegisterClasses(SingletonRegisters); 1011 1012 // Build info for the user defined assembly operand classes. 1013 BuildOperandClasses(); 1014 1015 // Build the information about matchables. 1016 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(), 1017 ie = Matchables.end(); it != ie; ++it) { 1018 MatchableInfo *II = *it; 1019 1020 // Parse the tokens after the mnemonic. 1021 for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) { 1022 MatchableInfo::Operand &Op = II->AsmOperands[i]; 1023 StringRef Token = Op.Token; 1024 1025 // Check for singleton registers. 1026 if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) { 1027 Op.Class = RegisterClasses[RegRecord]; 1028 assert(Op.Class && Op.Class->Registers.size() == 1 && 1029 "Unexpected class for singleton register"); 1030 continue; 1031 } 1032 1033 // Check for simple tokens. 1034 if (Token[0] != '$') { 1035 Op.Class = getTokenClass(Token); 1036 continue; 1037 } 1038 1039 // Otherwise this is an operand reference. 1040 StringRef OperandName; 1041 if (Token[1] == '{') 1042 OperandName = Token.substr(2, Token.size() - 3); 1043 else 1044 OperandName = Token.substr(1); 1045 1046 // Map this token to an operand. FIXME: Move elsewhere. 1047 unsigned Idx; 1048 if (!II->OperandList.hasOperandNamed(OperandName, Idx)) 1049 throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + 1050 OperandName.str() + "'"); 1051 1052 // FIXME: This is annoying, the named operand may be tied (e.g., 1053 // XCHG8rm). What we want is the untied operand, which we now have to 1054 // grovel for. Only worry about this for single entry operands, we have to 1055 // clean this up anyway. 1056 const CGIOperandList::OperandInfo *OI = &II->OperandList[Idx]; 1057 if (OI->Constraints[0].isTied()) { 1058 unsigned TiedOp = OI->Constraints[0].getTiedOperand(); 1059 1060 // The tied operand index is an MIOperand index, find the operand that 1061 // contains it. 1062 for (unsigned i = 0, e = II->OperandList.size(); i != e; ++i) { 1063 if (II->OperandList[i].MIOperandNo == TiedOp) { 1064 OI = &II->OperandList[i]; 1065 break; 1066 } 1067 } 1068 1069 assert(OI && "Unable to find tied operand target!"); 1070 } 1071 1072 Op.Class = getOperandClass(Token, *OI); 1073 Op.OperandInfo = OI; 1074 } 1075 } 1076 1077 // Reorder classes so that classes preceed super classes. 1078 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>()); 1079} 1080 1081static std::pair<unsigned, unsigned> * 1082GetTiedOperandAtIndex(SmallVectorImpl<std::pair<unsigned, unsigned> > &List, 1083 unsigned Index) { 1084 for (unsigned i = 0, e = List.size(); i != e; ++i) 1085 if (Index == List[i].first) 1086 return &List[i]; 1087 1088 return 0; 1089} 1090 1091static void EmitConvertToMCInst(CodeGenTarget &Target, 1092 std::vector<MatchableInfo*> &Infos, 1093 raw_ostream &OS) { 1094 // Write the convert function to a separate stream, so we can drop it after 1095 // the enum. 1096 std::string ConvertFnBody; 1097 raw_string_ostream CvtOS(ConvertFnBody); 1098 1099 // Function we have already generated. 1100 std::set<std::string> GeneratedFns; 1101 1102 // Start the unified conversion function. 1103 1104 CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, " 1105 << "unsigned Opcode,\n" 1106 << " const SmallVectorImpl<MCParsedAsmOperand*" 1107 << "> &Operands) {\n"; 1108 CvtOS << " Inst.setOpcode(Opcode);\n"; 1109 CvtOS << " switch (Kind) {\n"; 1110 CvtOS << " default:\n"; 1111 1112 // Start the enum, which we will generate inline. 1113 1114 OS << "// Unified function for converting operants to MCInst instances.\n\n"; 1115 OS << "enum ConversionKind {\n"; 1116 1117 // TargetOperandClass - This is the target's operand class, like X86Operand. 1118 std::string TargetOperandClass = Target.getName() + "Operand"; 1119 1120 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(), 1121 ie = Infos.end(); it != ie; ++it) { 1122 MatchableInfo &II = **it; 1123 1124 // Order the (class) operands by the order to convert them into an MCInst. 1125 SmallVector<std::pair<unsigned, unsigned>, 4> MIOperandList; 1126 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 1127 MatchableInfo::Operand &Op = II.AsmOperands[i]; 1128 if (Op.OperandInfo) 1129 MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i)); 1130 } 1131 1132 // Find any tied operands. 1133 SmallVector<std::pair<unsigned, unsigned>, 4> TiedOperands; 1134 for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { 1135 const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i]; 1136 for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) { 1137 const CGIOperandList::ConstraintInfo &CI = OpInfo.Constraints[j]; 1138 if (CI.isTied()) 1139 TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j, 1140 CI.getTiedOperand())); 1141 } 1142 } 1143 1144 array_pod_sort(MIOperandList.begin(), MIOperandList.end()); 1145 1146 // Compute the total number of operands. 1147 unsigned NumMIOperands = 0; 1148 for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { 1149 const CGIOperandList::OperandInfo &OI = II.OperandList[i]; 1150 NumMIOperands = std::max(NumMIOperands, 1151 OI.MIOperandNo + OI.MINumOperands); 1152 } 1153 1154 // Build the conversion function signature. 1155 std::string Signature = "Convert"; 1156 unsigned CurIndex = 0; 1157 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { 1158 MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; 1159 assert(CurIndex <= Op.OperandInfo->MIOperandNo && 1160 "Duplicate match for instruction operand!"); 1161 1162 // Skip operands which weren't matched by anything, this occurs when the 1163 // .td file encodes "implicit" operands as explicit ones. 1164 // 1165 // FIXME: This should be removed from the MCInst structure. 1166 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { 1167 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands, 1168 CurIndex); 1169 if (!Tie) 1170 Signature += "__Imp"; 1171 else 1172 Signature += "__Tie" + utostr(Tie->second); 1173 } 1174 1175 Signature += "__"; 1176 1177 // Registers are always converted the same, don't duplicate the conversion 1178 // function based on them. 1179 // 1180 // FIXME: We could generalize this based on the render method, if it 1181 // mattered. 1182 if (Op.Class->isRegisterClass()) 1183 Signature += "Reg"; 1184 else 1185 Signature += Op.Class->ClassName; 1186 Signature += utostr(Op.OperandInfo->MINumOperands); 1187 Signature += "_" + utostr(MIOperandList[i].second); 1188 1189 CurIndex += Op.OperandInfo->MINumOperands; 1190 } 1191 1192 // Add any trailing implicit operands. 1193 for (; CurIndex != NumMIOperands; ++CurIndex) { 1194 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands, 1195 CurIndex); 1196 if (!Tie) 1197 Signature += "__Imp"; 1198 else 1199 Signature += "__Tie" + utostr(Tie->second); 1200 } 1201 1202 II.ConversionFnKind = Signature; 1203 1204 // Check if we have already generated this signature. 1205 if (!GeneratedFns.insert(Signature).second) 1206 continue; 1207 1208 // If not, emit it now. 1209 1210 // Add to the enum list. 1211 OS << " " << Signature << ",\n"; 1212 1213 // And to the convert function. 1214 CvtOS << " case " << Signature << ":\n"; 1215 CurIndex = 0; 1216 for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { 1217 MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; 1218 1219 // Add the implicit operands. 1220 for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { 1221 // See if this is a tied operand. 1222 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands, 1223 CurIndex); 1224 1225 if (!Tie) { 1226 // If not, this is some implicit operand. Just assume it is a register 1227 // for now. 1228 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; 1229 } else { 1230 // Copy the tied operand. 1231 assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); 1232 CvtOS << " Inst.addOperand(Inst.getOperand(" 1233 << Tie->second << "));\n"; 1234 } 1235 } 1236 1237 CvtOS << " ((" << TargetOperandClass << "*)Operands[" 1238 << MIOperandList[i].second 1239 << "+1])->" << Op.Class->RenderMethod 1240 << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; 1241 CurIndex += Op.OperandInfo->MINumOperands; 1242 } 1243 1244 // And add trailing implicit operands. 1245 for (; CurIndex != NumMIOperands; ++CurIndex) { 1246 std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands, 1247 CurIndex); 1248 1249 if (!Tie) { 1250 // If not, this is some implicit operand. Just assume it is a register 1251 // for now. 1252 CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; 1253 } else { 1254 // Copy the tied operand. 1255 assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); 1256 CvtOS << " Inst.addOperand(Inst.getOperand(" 1257 << Tie->second << "));\n"; 1258 } 1259 } 1260 1261 CvtOS << " return;\n"; 1262 } 1263 1264 // Finish the convert function. 1265 1266 CvtOS << " }\n"; 1267 CvtOS << "}\n\n"; 1268 1269 // Finish the enum, and drop the convert function after it. 1270 1271 OS << " NumConversionVariants\n"; 1272 OS << "};\n\n"; 1273 1274 OS << CvtOS.str(); 1275} 1276 1277/// EmitMatchClassEnumeration - Emit the enumeration for match class kinds. 1278static void EmitMatchClassEnumeration(CodeGenTarget &Target, 1279 std::vector<ClassInfo*> &Infos, 1280 raw_ostream &OS) { 1281 OS << "namespace {\n\n"; 1282 1283 OS << "/// MatchClassKind - The kinds of classes which participate in\n" 1284 << "/// instruction matching.\n"; 1285 OS << "enum MatchClassKind {\n"; 1286 OS << " InvalidMatchClass = 0,\n"; 1287 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1288 ie = Infos.end(); it != ie; ++it) { 1289 ClassInfo &CI = **it; 1290 OS << " " << CI.Name << ", // "; 1291 if (CI.Kind == ClassInfo::Token) { 1292 OS << "'" << CI.ValueName << "'\n"; 1293 } else if (CI.isRegisterClass()) { 1294 if (!CI.ValueName.empty()) 1295 OS << "register class '" << CI.ValueName << "'\n"; 1296 else 1297 OS << "derived register class\n"; 1298 } else { 1299 OS << "user defined class '" << CI.ValueName << "'\n"; 1300 } 1301 } 1302 OS << " NumMatchClassKinds\n"; 1303 OS << "};\n\n"; 1304 1305 OS << "}\n\n"; 1306} 1307 1308/// EmitClassifyOperand - Emit the function to classify an operand. 1309static void EmitClassifyOperand(AsmMatcherInfo &Info, 1310 raw_ostream &OS) { 1311 OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n" 1312 << " " << Info.Target.getName() << "Operand &Operand = *(" 1313 << Info.Target.getName() << "Operand*)GOp;\n"; 1314 1315 // Classify tokens. 1316 OS << " if (Operand.isToken())\n"; 1317 OS << " return MatchTokenString(Operand.getToken());\n\n"; 1318 1319 // Classify registers. 1320 // 1321 // FIXME: Don't hardcode isReg, getReg. 1322 OS << " if (Operand.isReg()) {\n"; 1323 OS << " switch (Operand.getReg()) {\n"; 1324 OS << " default: return InvalidMatchClass;\n"; 1325 for (std::map<Record*, ClassInfo*>::iterator 1326 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end(); 1327 it != ie; ++it) 1328 OS << " case " << Info.Target.getName() << "::" 1329 << it->first->getName() << ": return " << it->second->Name << ";\n"; 1330 OS << " }\n"; 1331 OS << " }\n\n"; 1332 1333 // Classify user defined operands. 1334 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(), 1335 ie = Info.Classes.end(); it != ie; ++it) { 1336 ClassInfo &CI = **it; 1337 1338 if (!CI.isUserClass()) 1339 continue; 1340 1341 OS << " // '" << CI.ClassName << "' class"; 1342 if (!CI.SuperClasses.empty()) { 1343 OS << ", subclass of "; 1344 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) { 1345 if (i) OS << ", "; 1346 OS << "'" << CI.SuperClasses[i]->ClassName << "'"; 1347 assert(CI < *CI.SuperClasses[i] && "Invalid class relation!"); 1348 } 1349 } 1350 OS << "\n"; 1351 1352 OS << " if (Operand." << CI.PredicateMethod << "()) {\n"; 1353 1354 // Validate subclass relationships. 1355 if (!CI.SuperClasses.empty()) { 1356 for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) 1357 OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod 1358 << "() && \"Invalid class relationship!\");\n"; 1359 } 1360 1361 OS << " return " << CI.Name << ";\n"; 1362 OS << " }\n\n"; 1363 } 1364 OS << " return InvalidMatchClass;\n"; 1365 OS << "}\n\n"; 1366} 1367 1368/// EmitIsSubclass - Emit the subclass predicate function. 1369static void EmitIsSubclass(CodeGenTarget &Target, 1370 std::vector<ClassInfo*> &Infos, 1371 raw_ostream &OS) { 1372 OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n"; 1373 OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n"; 1374 OS << " if (A == B)\n"; 1375 OS << " return true;\n\n"; 1376 1377 OS << " switch (A) {\n"; 1378 OS << " default:\n"; 1379 OS << " return false;\n"; 1380 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1381 ie = Infos.end(); it != ie; ++it) { 1382 ClassInfo &A = **it; 1383 1384 if (A.Kind != ClassInfo::Token) { 1385 std::vector<StringRef> SuperClasses; 1386 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1387 ie = Infos.end(); it != ie; ++it) { 1388 ClassInfo &B = **it; 1389 1390 if (&A != &B && A.isSubsetOf(B)) 1391 SuperClasses.push_back(B.Name); 1392 } 1393 1394 if (SuperClasses.empty()) 1395 continue; 1396 1397 OS << "\n case " << A.Name << ":\n"; 1398 1399 if (SuperClasses.size() == 1) { 1400 OS << " return B == " << SuperClasses.back() << ";\n"; 1401 continue; 1402 } 1403 1404 OS << " switch (B) {\n"; 1405 OS << " default: return false;\n"; 1406 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) 1407 OS << " case " << SuperClasses[i] << ": return true;\n"; 1408 OS << " }\n"; 1409 } 1410 } 1411 OS << " }\n"; 1412 OS << "}\n\n"; 1413} 1414 1415 1416 1417/// EmitMatchTokenString - Emit the function to match a token string to the 1418/// appropriate match class value. 1419static void EmitMatchTokenString(CodeGenTarget &Target, 1420 std::vector<ClassInfo*> &Infos, 1421 raw_ostream &OS) { 1422 // Construct the match list. 1423 std::vector<StringMatcher::StringPair> Matches; 1424 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1425 ie = Infos.end(); it != ie; ++it) { 1426 ClassInfo &CI = **it; 1427 1428 if (CI.Kind == ClassInfo::Token) 1429 Matches.push_back(StringMatcher::StringPair(CI.ValueName, 1430 "return " + CI.Name + ";")); 1431 } 1432 1433 OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n"; 1434 1435 StringMatcher("Name", Matches, OS).Emit(); 1436 1437 OS << " return InvalidMatchClass;\n"; 1438 OS << "}\n\n"; 1439} 1440 1441/// EmitMatchRegisterName - Emit the function to match a string to the target 1442/// specific register enum. 1443static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser, 1444 raw_ostream &OS) { 1445 // Construct the match list. 1446 std::vector<StringMatcher::StringPair> Matches; 1447 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { 1448 const CodeGenRegister &Reg = Target.getRegisters()[i]; 1449 if (Reg.TheDef->getValueAsString("AsmName").empty()) 1450 continue; 1451 1452 Matches.push_back(StringMatcher::StringPair( 1453 Reg.TheDef->getValueAsString("AsmName"), 1454 "return " + utostr(i + 1) + ";")); 1455 } 1456 1457 OS << "static unsigned MatchRegisterName(StringRef Name) {\n"; 1458 1459 StringMatcher("Name", Matches, OS).Emit(); 1460 1461 OS << " return 0;\n"; 1462 OS << "}\n\n"; 1463} 1464 1465/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag 1466/// definitions. 1467static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info, 1468 raw_ostream &OS) { 1469 OS << "// Flags for subtarget features that participate in " 1470 << "instruction matching.\n"; 1471 OS << "enum SubtargetFeatureFlag {\n"; 1472 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 1473 it = Info.SubtargetFeatures.begin(), 1474 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 1475 SubtargetFeatureInfo &SFI = *it->second; 1476 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; 1477 } 1478 OS << " Feature_None = 0\n"; 1479 OS << "};\n\n"; 1480} 1481 1482/// EmitComputeAvailableFeatures - Emit the function to compute the list of 1483/// available features given a subtarget. 1484static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info, 1485 raw_ostream &OS) { 1486 std::string ClassName = 1487 Info.AsmParser->getValueAsString("AsmParserClassName"); 1488 1489 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" 1490 << "ComputeAvailableFeatures(const " << Info.Target.getName() 1491 << "Subtarget *Subtarget) const {\n"; 1492 OS << " unsigned Features = 0;\n"; 1493 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 1494 it = Info.SubtargetFeatures.begin(), 1495 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 1496 SubtargetFeatureInfo &SFI = *it->second; 1497 OS << " if (" << SFI.TheDef->getValueAsString("CondString") 1498 << ")\n"; 1499 OS << " Features |= " << SFI.getEnumName() << ";\n"; 1500 } 1501 OS << " return Features;\n"; 1502 OS << "}\n\n"; 1503} 1504 1505static std::string GetAliasRequiredFeatures(Record *R, 1506 const AsmMatcherInfo &Info) { 1507 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates"); 1508 std::string Result; 1509 unsigned NumFeatures = 0; 1510 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { 1511 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); 1512 1513 if (F == 0) 1514 throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + 1515 "' is not marked as an AssemblerPredicate!"); 1516 1517 if (NumFeatures) 1518 Result += '|'; 1519 1520 Result += F->getEnumName(); 1521 ++NumFeatures; 1522 } 1523 1524 if (NumFeatures > 1) 1525 Result = '(' + Result + ')'; 1526 return Result; 1527} 1528 1529/// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions, 1530/// emit a function for them and return true, otherwise return false. 1531static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { 1532 std::vector<Record*> Aliases = 1533 Records.getAllDerivedDefinitions("MnemonicAlias"); 1534 if (Aliases.empty()) return false; 1535 1536 OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, " 1537 "unsigned Features) {\n"; 1538 1539 // Keep track of all the aliases from a mnemonic. Use an std::map so that the 1540 // iteration order of the map is stable. 1541 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic; 1542 1543 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { 1544 Record *R = Aliases[i]; 1545 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); 1546 } 1547 1548 // Process each alias a "from" mnemonic at a time, building the code executed 1549 // by the string remapper. 1550 std::vector<StringMatcher::StringPair> Cases; 1551 for (std::map<std::string, std::vector<Record*> >::iterator 1552 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end(); 1553 I != E; ++I) { 1554 const std::vector<Record*> &ToVec = I->second; 1555 1556 // Loop through each alias and emit code that handles each case. If there 1557 // are two instructions without predicates, emit an error. If there is one, 1558 // emit it last. 1559 std::string MatchCode; 1560 int AliasWithNoPredicate = -1; 1561 1562 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { 1563 Record *R = ToVec[i]; 1564 std::string FeatureMask = GetAliasRequiredFeatures(R, Info); 1565 1566 // If this unconditionally matches, remember it for later and diagnose 1567 // duplicates. 1568 if (FeatureMask.empty()) { 1569 if (AliasWithNoPredicate != -1) { 1570 // We can't have two aliases from the same mnemonic with no predicate. 1571 PrintError(ToVec[AliasWithNoPredicate]->getLoc(), 1572 "two MnemonicAliases with the same 'from' mnemonic!"); 1573 throw TGError(R->getLoc(), "this is the other MnemonicAlias."); 1574 } 1575 1576 AliasWithNoPredicate = i; 1577 continue; 1578 } 1579 1580 if (!MatchCode.empty()) 1581 MatchCode += "else "; 1582 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; 1583 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; 1584 } 1585 1586 if (AliasWithNoPredicate != -1) { 1587 Record *R = ToVec[AliasWithNoPredicate]; 1588 if (!MatchCode.empty()) 1589 MatchCode += "else\n "; 1590 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; 1591 } 1592 1593 MatchCode += "return;"; 1594 1595 Cases.push_back(std::make_pair(I->first, MatchCode)); 1596 } 1597 1598 1599 StringMatcher("Mnemonic", Cases, OS).Emit(); 1600 OS << "}\n"; 1601 1602 return true; 1603} 1604 1605void AsmMatcherEmitter::run(raw_ostream &OS) { 1606 CodeGenTarget Target; 1607 Record *AsmParser = Target.getAsmParser(); 1608 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName"); 1609 1610 // Compute the information on the instructions to match. 1611 AsmMatcherInfo Info(AsmParser, Target); 1612 Info.BuildInfo(); 1613 1614 // Sort the instruction table using the partial order on classes. We use 1615 // stable_sort to ensure that ambiguous instructions are still 1616 // deterministically ordered. 1617 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(), 1618 less_ptr<MatchableInfo>()); 1619 1620 DEBUG_WITH_TYPE("instruction_info", { 1621 for (std::vector<MatchableInfo*>::iterator 1622 it = Info.Matchables.begin(), ie = Info.Matchables.end(); 1623 it != ie; ++it) 1624 (*it)->dump(); 1625 }); 1626 1627 // Check for ambiguous matchables. 1628 DEBUG_WITH_TYPE("ambiguous_instrs", { 1629 unsigned NumAmbiguous = 0; 1630 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) { 1631 for (unsigned j = i + 1; j != e; ++j) { 1632 MatchableInfo &A = *Info.Matchables[i]; 1633 MatchableInfo &B = *Info.Matchables[j]; 1634 1635 if (A.CouldMatchAmiguouslyWith(B)) { 1636 errs() << "warning: ambiguous matchables:\n"; 1637 A.dump(); 1638 errs() << "\nis incomparable with:\n"; 1639 B.dump(); 1640 errs() << "\n\n"; 1641 ++NumAmbiguous; 1642 } 1643 } 1644 } 1645 if (NumAmbiguous) 1646 errs() << "warning: " << NumAmbiguous 1647 << " ambiguous matchables!\n"; 1648 }); 1649 1650 // Write the output. 1651 1652 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS); 1653 1654 // Information for the class declaration. 1655 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; 1656 OS << "#undef GET_ASSEMBLER_HEADER\n"; 1657 OS << " // This should be included into the middle of the declaration of \n"; 1658 OS << " // your subclasses implementation of TargetAsmParser.\n"; 1659 OS << " unsigned ComputeAvailableFeatures(const " << 1660 Target.getName() << "Subtarget *Subtarget) const;\n"; 1661 OS << " enum MatchResultTy {\n"; 1662 OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n"; 1663 OS << " Match_MissingFeature\n"; 1664 OS << " };\n"; 1665 OS << " MatchResultTy MatchInstructionImpl(const " 1666 << "SmallVectorImpl<MCParsedAsmOperand*>" 1667 << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n"; 1668 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; 1669 1670 1671 1672 1673 OS << "\n#ifdef GET_REGISTER_MATCHER\n"; 1674 OS << "#undef GET_REGISTER_MATCHER\n\n"; 1675 1676 // Emit the subtarget feature enumeration. 1677 EmitSubtargetFeatureFlagEnumeration(Info, OS); 1678 1679 // Emit the function to match a register name to number. 1680 EmitMatchRegisterName(Target, AsmParser, OS); 1681 1682 OS << "#endif // GET_REGISTER_MATCHER\n\n"; 1683 1684 1685 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n"; 1686 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n"; 1687 1688 // Generate the function that remaps for mnemonic aliases. 1689 bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info); 1690 1691 // Generate the unified function to convert operands into an MCInst. 1692 EmitConvertToMCInst(Target, Info.Matchables, OS); 1693 1694 // Emit the enumeration for classes which participate in matching. 1695 EmitMatchClassEnumeration(Target, Info.Classes, OS); 1696 1697 // Emit the routine to match token strings to their match class. 1698 EmitMatchTokenString(Target, Info.Classes, OS); 1699 1700 // Emit the routine to classify an operand. 1701 EmitClassifyOperand(Info, OS); 1702 1703 // Emit the subclass predicate routine. 1704 EmitIsSubclass(Target, Info.Classes, OS); 1705 1706 // Emit the available features compute function. 1707 EmitComputeAvailableFeatures(Info, OS); 1708 1709 1710 size_t MaxNumOperands = 0; 1711 for (std::vector<MatchableInfo*>::const_iterator it = 1712 Info.Matchables.begin(), ie = Info.Matchables.end(); 1713 it != ie; ++it) 1714 MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size()); 1715 1716 1717 // Emit the static match table; unused classes get initalized to 0 which is 1718 // guaranteed to be InvalidMatchClass. 1719 // 1720 // FIXME: We can reduce the size of this table very easily. First, we change 1721 // it so that store the kinds in separate bit-fields for each index, which 1722 // only needs to be the max width used for classes at that index (we also need 1723 // to reject based on this during classification). If we then make sure to 1724 // order the match kinds appropriately (putting mnemonics last), then we 1725 // should only end up using a few bits for each class, especially the ones 1726 // following the mnemonic. 1727 OS << "namespace {\n"; 1728 OS << " struct MatchEntry {\n"; 1729 OS << " unsigned Opcode;\n"; 1730 OS << " const char *Mnemonic;\n"; 1731 OS << " ConversionKind ConvertFn;\n"; 1732 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; 1733 OS << " unsigned RequiredFeatures;\n"; 1734 OS << " };\n\n"; 1735 1736 OS << "// Predicate for searching for an opcode.\n"; 1737 OS << " struct LessOpcode {\n"; 1738 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n"; 1739 OS << " return StringRef(LHS.Mnemonic) < RHS;\n"; 1740 OS << " }\n"; 1741 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n"; 1742 OS << " return LHS < StringRef(RHS.Mnemonic);\n"; 1743 OS << " }\n"; 1744 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n"; 1745 OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n"; 1746 OS << " }\n"; 1747 OS << " };\n"; 1748 1749 OS << "} // end anonymous namespace.\n\n"; 1750 1751 OS << "static const MatchEntry MatchTable[" 1752 << Info.Matchables.size() << "] = {\n"; 1753 1754 for (std::vector<MatchableInfo*>::const_iterator it = 1755 Info.Matchables.begin(), ie = Info.Matchables.end(); 1756 it != ie; ++it) { 1757 MatchableInfo &II = **it; 1758 1759 OS << " { " << Target.getName() << "::" << II.InstrName 1760 << ", \"" << II.Mnemonic << "\"" 1761 << ", " << II.ConversionFnKind << ", { "; 1762 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 1763 MatchableInfo::Operand &Op = II.AsmOperands[i]; 1764 1765 if (i) OS << ", "; 1766 OS << Op.Class->Name; 1767 } 1768 OS << " }, "; 1769 1770 // Write the required features mask. 1771 if (!II.RequiredFeatures.empty()) { 1772 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { 1773 if (i) OS << "|"; 1774 OS << II.RequiredFeatures[i]->getEnumName(); 1775 } 1776 } else 1777 OS << "0"; 1778 1779 OS << "},\n"; 1780 } 1781 1782 OS << "};\n\n"; 1783 1784 // Finally, build the match function. 1785 OS << Target.getName() << ClassName << "::MatchResultTy " 1786 << Target.getName() << ClassName << "::\n" 1787 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>" 1788 << " &Operands,\n"; 1789 OS << " MCInst &Inst, unsigned &ErrorInfo) {\n"; 1790 1791 // Emit code to get the available features. 1792 OS << " // Get the current feature set.\n"; 1793 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; 1794 1795 OS << " // Get the instruction mnemonic, which is the first token.\n"; 1796 OS << " StringRef Mnemonic = ((" << Target.getName() 1797 << "Operand*)Operands[0])->getToken();\n\n"; 1798 1799 if (HasMnemonicAliases) { 1800 OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; 1801 OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; 1802 } 1803 1804 // Emit code to compute the class list for this operand vector. 1805 OS << " // Eliminate obvious mismatches.\n"; 1806 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; 1807 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n"; 1808 OS << " return Match_InvalidOperand;\n"; 1809 OS << " }\n\n"; 1810 1811 OS << " // Compute the class list for this operand vector.\n"; 1812 OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; 1813 OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n"; 1814 OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n"; 1815 1816 OS << " // Check for invalid operands before matching.\n"; 1817 OS << " if (Classes[i-1] == InvalidMatchClass) {\n"; 1818 OS << " ErrorInfo = i;\n"; 1819 OS << " return Match_InvalidOperand;\n"; 1820 OS << " }\n"; 1821 OS << " }\n\n"; 1822 1823 OS << " // Mark unused classes.\n"; 1824 OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; " 1825 << "i != e; ++i)\n"; 1826 OS << " Classes[i] = InvalidMatchClass;\n\n"; 1827 1828 OS << " // Some state to try to produce better error messages.\n"; 1829 OS << " bool HadMatchOtherThanFeatures = false;\n\n"; 1830 OS << " // Set ErrorInfo to the operand that mismatches if it is \n"; 1831 OS << " // wrong for all instances of the instruction.\n"; 1832 OS << " ErrorInfo = ~0U;\n"; 1833 1834 // Emit code to search the table. 1835 OS << " // Search the table.\n"; 1836 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; 1837 OS << " std::equal_range(MatchTable, MatchTable+" 1838 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n"; 1839 1840 OS << " // Return a more specific error code if no mnemonics match.\n"; 1841 OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; 1842 OS << " return Match_MnemonicFail;\n\n"; 1843 1844 OS << " for (const MatchEntry *it = MnemonicRange.first, " 1845 << "*ie = MnemonicRange.second;\n"; 1846 OS << " it != ie; ++it) {\n"; 1847 1848 OS << " // equal_range guarantees that instruction mnemonic matches.\n"; 1849 OS << " assert(Mnemonic == it->Mnemonic);\n"; 1850 1851 // Emit check that the subclasses match. 1852 OS << " bool OperandsValid = true;\n"; 1853 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; 1854 OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n"; 1855 OS << " continue;\n"; 1856 OS << " // If this operand is broken for all of the instances of this\n"; 1857 OS << " // mnemonic, keep track of it so we can report loc info.\n"; 1858 OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n"; 1859 OS << " ErrorInfo = i+1;\n"; 1860 OS << " else\n"; 1861 OS << " ErrorInfo = ~0U;"; 1862 OS << " // Otherwise, just reject this instance of the mnemonic.\n"; 1863 OS << " OperandsValid = false;\n"; 1864 OS << " break;\n"; 1865 OS << " }\n\n"; 1866 1867 OS << " if (!OperandsValid) continue;\n"; 1868 1869 // Emit check that the required features are available. 1870 OS << " if ((AvailableFeatures & it->RequiredFeatures) " 1871 << "!= it->RequiredFeatures) {\n"; 1872 OS << " HadMatchOtherThanFeatures = true;\n"; 1873 OS << " continue;\n"; 1874 OS << " }\n"; 1875 1876 OS << "\n"; 1877 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; 1878 1879 // Call the post-processing function, if used. 1880 std::string InsnCleanupFn = 1881 AsmParser->getValueAsString("AsmParserInstCleanup"); 1882 if (!InsnCleanupFn.empty()) 1883 OS << " " << InsnCleanupFn << "(Inst);\n"; 1884 1885 OS << " return Match_Success;\n"; 1886 OS << " }\n\n"; 1887 1888 OS << " // Okay, we had no match. Try to return a useful error code.\n"; 1889 OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n"; 1890 OS << " return Match_InvalidOperand;\n"; 1891 OS << "}\n\n"; 1892 1893 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; 1894} 1895