15a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 25a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * @file daemon/opd_ibs_macro.h 37a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * AMD Instruction Based Sampling (IBS) related macro. 45a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 57a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * @remark Copyright 2008-2010 OProfile authors 65a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * @remark Read the file COPYING 75a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 85a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * @author Jason Yeh <jason.yeh@amd.com> 95a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * @author Paul Drongowski <paul.drongowski@amd.com> 105a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> 115a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * Copyright (c) 2008 Advanced Micro Devices, Inc. 125a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 135a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 145a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#ifndef OPD_IBS_MACRO_H 155a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define OPD_IBS_MACRO_H 165a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 175a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 185a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The following defines are bit masks that are used to select 197a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * IBS fetch event flags and values at the 207a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * MSRC001_1030 IBS Fetch Control Register (IbsFetchCtl) 215a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 225a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_LATENCY 0x0000ffff 235a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_COMPLETE 0x00040000 245a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_IC_MISS 0x00080000 255a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_PHY_ADDR 0x00100000 265a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_PG_SIZE 0x00600000 275a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_L1_MISS 0x00800000 285a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_L2_MISS 0x01000000 295a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define FETCH_MASK_KILLED \ 305a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng (FETCH_MASK_L1_MISS|FETCH_MASK_L2_MISS|FETCH_MASK_PHY_ADDR|\ 315a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng FETCH_MASK_COMPLETE|FETCH_MASK_IC_MISS) 325a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 335a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 345a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 355a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The following defines are bit masks that are used to select 365a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * IBS op event flags and values at the MSR level. 375a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 387a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 397a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown/* MSRC001_1035 IBS Op Data Register (IbsOpData) */ 405a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_RETIRE 0x0000ffff 417a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define MASK_RIP_INVALID 0x00000040 425a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_BRN_RET 0x00000020 435a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_BRN_MISP 0x00000010 445a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_BRN_TAKEN 0x00000008 455a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_RETURN 0x00000004 465a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_MISP_RETURN 0x00000002 475a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define BR_MASK_BRN_RESYNC 0x00000001 485a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 497a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown/* MSRC001_1036 IBS Op Data Register (IbsOpData2) */ 505a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define NB_MASK_L3_STATE 0x00000020 515a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define NB_MASK_REQ_DST_PROC 0x00000010 525a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define NB_MASK_REQ_DATA_SRC 0x00000007 535a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 547a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown/* MSRC001_1037 IBS Op Data Register (IbsOpData3) */ 555a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_L2_HIT_1G 0x00080000 565a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_PHY_ADDR_VALID 0x00040000 575a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_LIN_ADDR_VALID 0x00020000 585a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_MAB_HIT 0x00010000 595a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_LOCKED_OP 0x00008000 607a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define DC_MASK_UC_MEM_ACCESS 0x00004000 617a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define DC_MASK_WC_MEM_ACCESS 0x00002000 625a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_ST_TO_LD_CANCEL 0x00001000 635a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_ST_TO_LD_FOR 0x00000800 645a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_ST_BANK_CONFLICT 0x00000400 655a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_LD_BANK_CONFLICT 0x00000200 665a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_MISALIGN_ACCESS 0x00000100 675a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_DC_MISS 0x00000080 685a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_L2_HIT_2M 0x00000040 695a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_L1_HIT_1G 0x00000020 705a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_L1_HIT_2M 0x00000010 715a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_L2_TLB_MISS 0x00000008 725a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_L1_TLB_MISS 0x00000004 735a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_STORE_OP 0x00000002 745a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DC_MASK_LOAD_OP 0x00000001 755a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 765a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 775a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 785a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * IBS derived events: 795a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 805a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * IBS derived events are identified by event select values which are 815a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * similar to the event select values that identify performance monitoring 825a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * counter (PMC) events. Event select values for IBS derived events begin 835a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * at 0xf000. 845a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 855a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The definitions in this file *must* match definitions 867a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * of IBS derived events. More information 875a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * about IBS derived events is given in the Software Oprimization 887a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * Guide. 895a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 905a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 915a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 925a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The following defines associate a 16-bit select value with an IBS 935a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * derived fetch event. 945a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 955a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_ALL 0xf000 965a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_KILLED 0xf001 975a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_ATTEMPTED 0xf002 985a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_COMPLETED 0xf003 995a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_ABORTED 0xf004 1005a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_L1_ITLB_HIT 0xf005 1015a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_ITLB_L1M_L2H 0xf006 1025a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_ITLB_L1M_L2M 0xf007 1035a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_IC_MISS 0xf008 1045a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_IC_HIT 0xf009 1055a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_4K_PAGE 0xf00a 1065a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_2M_PAGE 0xf00b 1075a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_1G_PAGE 0xf00c 1085a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_XX_PAGE 0xf00d 1095a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_FETCH_LATENCY 0xf00e 1105a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1115a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_BASE 0xf000 1125a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_END 0xf00e 1135a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_MAX (IBS_FETCH_END - IBS_FETCH_BASE + 1) 1145a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IS_IBS_FETCH(x) (IBS_FETCH_BASE <= x && x <= IBS_FETCH_END) 1155a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_OFFSET(x) (x - IBS_FETCH_BASE) 1167a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define CHECK_FETCH_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_FETCH_OFFSET(x))) 1177a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 1185a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1195a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 1205a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The following defines associate a 16-bit select value with an IBS 1215a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * derived branch/return macro-op event. 1225a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 1235a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_OP_ALL 0xf100 1245a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_OP_TAG_TO_RETIRE 0xf101 1255a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_OP_COMP_TO_RETIRE 0xf102 1265a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_BRANCH_RETIRED 0xf103 1275a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_BRANCH_MISP 0xf104 1285a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_BRANCH_TAKEN 0xf105 1295a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_BRANCH_MISP_TAKEN 0xf106 1305a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_RETURN 0xf107 1315a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_RETURN_MISP 0xf108 1325a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_RESYNC 0xf109 1335a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1345a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_BASE 0xf100 1355a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_END 0xf109 1365a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_MAX (IBS_OP_END - IBS_OP_BASE + 1) 1375a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IS_IBS_OP(x) (IBS_OP_BASE <= x && x <= IBS_OP_END) 1385a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_OFFSET(x) (x - IBS_OP_BASE) 1397a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define CHECK_OP_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_OP_OFFSET(x))) 1407a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 1415a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1425a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 1435a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The following defines associate a 16-bit select value with an IBS 1445a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * derived load/store event. 1455a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 1465a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_ALL_OP 0xf200 1475a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_LOAD_OP 0xf201 1485a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_STORE_OP 0xf202 1495a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_DTLB_L1H 0xf203 1505a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_DTLB_L1M_L2H 0xf204 1515a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_DTLB_L1M_L2M 0xf205 1525a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_DC_MISS 0xf206 1535a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_DC_HIT 0xf207 1545a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_MISALIGNED 0xf208 1555a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_BNK_CONF_LOAD 0xf209 1565a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_BNK_CONF_STORE 0xf20a 1575a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_STL_FORWARDED 0xf20b 1585a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_STL_CANCELLED 0xf20c 1595a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_UC_MEM_ACCESS 0xf20d 1605a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_WC_MEM_ACCESS 0xf20e 1615a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_LOCKED_OP 0xf20f 1625a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_MAB_HIT 0xf210 1635a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L1_DTLB_4K 0xf211 1645a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L1_DTLB_2M 0xf212 1655a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L1_DTLB_1G 0xf213 1665a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L1_DTLB_RES 0xf214 1675a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L2_DTLB_4K 0xf215 1685a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L2_DTLB_2M 0xf216 1695a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L2_DTLB_1G 0xf217 1705a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_L2_DTLB_RES2 0xf218 1715a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_LS_DC_LOAD_LAT 0xf219 1725a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1735a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_LS_BASE 0xf200 1745a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_LS_END 0xf219 1755a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_LS_MAX (IBS_OP_LS_END - IBS_OP_LS_BASE + 1) 1765a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IS_IBS_OP_LS(x) (IBS_OP_LS_BASE <= x && x <= IBS_OP_LS_END) 1775a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_LS_OFFSET(x) (x - IBS_OP_LS_BASE) 1787a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define CHECK_OP_LS_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_OP_LS_OFFSET(x))) 1795a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1805a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1815a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 1825a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * The following defines associate a 16-bit select value with an IBS 1835a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * derived Northbridge (NB) event. 1845a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 1855a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_LOCAL 0xf240 1865a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_REMOTE 0xf241 1875a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_LOCAL_L3 0xf242 1885a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_LOCAL_CACHE 0xf243 1895a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_REMOTE_CACHE 0xf244 1905a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_LOCAL_DRAM 0xf245 1915a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_REMOTE_DRAM 0xf246 1925a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_LOCAL_OTHER 0xf247 1935a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_REMOTE_OTHER 0xf248 1945a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_CACHE_STATE_M 0xf249 1955a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_CACHE_STATE_O 0xf24a 1965a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_LOCAL_LATENCY 0xf24b 1975a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define DE_IBS_NB_REMOTE_LATENCY 0xf24c 1985a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 1995a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_BASE 0xf240 2005a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_END 0xf24c 2015a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_MAX (IBS_OP_NB_END - IBS_OP_NB_BASE + 1) 2025a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IS_IBS_OP_NB(x) (IBS_OP_NB_BASE <= x && x <= IBS_OP_NB_END) 2035a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_OFFSET(x) (x - IBS_OP_NB_BASE) 2047a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define CHECK_OP_NB_SELECTED_FLAG(x) if ( selected_flag & (1 << IBS_OP_NB_OFFSET(x))) 2055a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2065a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2075a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define OP_MAX_IBS_COUNTERS (IBS_FETCH_MAX + IBS_OP_MAX + IBS_OP_LS_MAX + IBS_OP_NB_MAX) 2085a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2095a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2105a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 2115a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * These macro decodes IBS hardware-level event flags and fields. 2125a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * Translation results are either zero (false) or non-zero (true), except 2135a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * the fetch latency, which is a 16-bit cycle count, and the fetch page size 2145a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * field, which is a 2-bit unsigned integer. 2155a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 2165a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2175a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bits 47:32 IbsFetchLat: instruction fetch latency */ 2185a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_FETCH_LATENCY(x) ((unsigned short)(x->ibs_fetch_ctl_high & FETCH_MASK_LATENCY)) 2195a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2205a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bit 50 IbsFetchComp: instruction fetch complete. */ 2215a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_FETCH_COMPLETION(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_COMPLETE) != 0) 2225a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2235a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bit 51 IbsIcMiss: instruction cache miss. */ 2245a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_INST_CACHE_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_IC_MISS) != 0) 2255a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2265a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bit 52 IbsPhyAddrValid: instruction fetch physical address valid. */ 2275a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_PHYS_ADDR_VALID(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_PHY_ADDR) != 0) 2285a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2297a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownenum IBSL1PAGESIZE { 2307a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown L1TLB4K = 0, 2317a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown L1TLB2M, 2327a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown L1TLB1G, 2337a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown L1TLB_INVALID 2347a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown}; 2357a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 2365a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bits 54:53 IbsL1TlbPgSz: instruction cache L1TLB page size. */ 2375a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_TLB_PAGE_SIZE(x) ((unsigned short)((x->ibs_fetch_ctl_high >> 21) & 0x3)) 2387a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_FETCH_TLB_PAGE_SIZE_4K(x) (IBS_FETCH_TLB_PAGE_SIZE(x) == L1TLB4K) 2397a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_FETCH_TLB_PAGE_SIZE_2M(x) (IBS_FETCH_TLB_PAGE_SIZE(x) == L1TLB2M) 2407a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_FETCH_TLB_PAGE_SIZE_1G(x) (IBS_FETCH_TLB_PAGE_SIZE(x) == L1TLB1G) 2415a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2425a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bit 55 IbsL1TlbMiss: instruction cache L1TLB miss. */ 2435a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_M_L1_TLB_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_L1_MISS) != 0) 2445a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2455a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** Bit 56 IbsL2TlbMiss: instruction cache L2TLB miss. */ 2465a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_L2_TLB_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_L2_MISS) != 0) 2475a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2485a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** A fetch is a killed fetch if all the masked bits are clear */ 2495a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_KILLED(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_KILLED) == 0) 2505a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2515a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_INST_CACHE_HIT(x) (IBS_FETCH_FETCH_COMPLETION(x) && !IBS_FETCH_INST_CACHE_MISS(x)) 2525a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2535a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_L1_TLB_HIT(x) (!IBS_FETCH_M_L1_TLB_MISS(x) && IBS_FETCH_PHYS_ADDR_VALID(x)) 2545a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2555a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_ITLB_L1M_L2H(x) (IBS_FETCH_M_L1_TLB_MISS(x) && !IBS_FETCH_L2_TLB_MISS(x)) 2565a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2575a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_FETCH_ITLB_L1M_L2M(x) (IBS_FETCH_M_L1_TLB_MISS(x) && IBS_FETCH_L2_TLB_MISS(x)) 2585a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2595a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2605a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 2615a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * These macros translates IBS op event data from its hardware-level 2625a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * representation .It hides the MSR layout of IBS op data. 2635a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 2645a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2655a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 2665a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * MSRC001_1035 IBS OP Data Register (IbsOpData) 2675a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 2685a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 15:0 IbsCompToRetCtr: macro-op completion to retire count 2695a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 2705a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_COM_TO_RETIRE_CYCLES(x) ((unsigned short)(x->ibs_op_data1_low & BR_MASK_RETIRE)) 2715a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2725a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 31:16 tag_to_retire_cycles : macro-op tag to retire count. */ 2735a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_TAG_TO_RETIRE_CYCLES(x) ((unsigned short)((x->ibs_op_data1_low >> 16) & BR_MASK_RETIRE)) 2745a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2755a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 32 op_branch_resync : resync macro-op. */ 2767a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_BRANCH_RESYNC(x) ((x->ibs_op_data1_high & BR_MASK_BRN_RESYNC) != 0) 2775a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2785a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 33 op_mispredict_return : mispredicted return macro-op. */ 2797a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_MISPREDICT_RETURN(x) ((x->ibs_op_data1_high & BR_MASK_MISP_RETURN) != 0) 2805a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2815a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 34 IbsOpReturn: return macro-op. */ 2827a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_RETURN(x) ((x->ibs_op_data1_high & BR_MASK_RETURN) != 0) 2835a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2845a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 35 IbsOpBrnTaken: taken branch macro-op. */ 2857a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_BRANCH_TAKEN(x) ((x->ibs_op_data1_high & BR_MASK_BRN_TAKEN) != 0) 2865a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2875a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 36 IbsOpBrnMisp: mispredicted branch macro-op. */ 2887a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_BRANCH_MISPREDICT(x) ((x->ibs_op_data1_high & BR_MASK_BRN_MISP) != 0) 2895a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2905a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 37 IbsOpBrnRet: branch macro-op retired. */ 2917a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_BRANCH_RETIRED(x) ((x->ibs_op_data1_high & BR_MASK_BRN_RET) != 0) 2927a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 2937a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown/** 38 IbsRipInvalid: RIP invalid. */ 2947a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_RIP_INVALID(x) ((x->ibs_op_data1_high & MASK_RIP_INVALID) != 0) 2955a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 2965a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 2975a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * MSRC001_1036 IBS Op Data 2 Register (IbsOpData2) 2985a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 2995a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 5 NbIbsReqCacheHitSt: IBS L3 cache state 3005a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 3015a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_IBS_CACHE_HIT_ST(x) ((x->ibs_op_data2_low & NB_MASK_L3_STATE) != 0) 3025a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3035a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 4 NbIbsReqDstProc: IBS request destination processor */ 3045a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_IBS_REQ_DST_PROC(x) ((x->ibs_op_data2_low & NB_MASK_REQ_DST_PROC) != 0) 3055a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3065a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 2:0 NbIbsReqSrc: Northbridge IBS request data source */ 3075a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_NB_IBS_REQ_SRC(x) ((unsigned char)(x->ibs_op_data2_low & NB_MASK_REQ_DATA_SRC)) 3085a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3097a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_NB_IBS_REQ_SRC_01(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x01) 3107a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 3117a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_NB_IBS_REQ_SRC_02(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x02) 3127a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 3137a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_NB_IBS_REQ_SRC_03(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x03) 3147a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 3157a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_NB_IBS_REQ_SRC_07(x) (IBS_OP_NB_IBS_REQ_SRC(x) == 0x07) 3167a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 3175a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 3185a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * MSRC001_1037 IBS Op Data3 Register 3195a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * 3207a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown * Bits 47:32 IbsDcMissLat 3215a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 3225a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_DC_MISS_LATENCY(x) ((unsigned short)(x->ibs_op_data3_high & 0xffff)) 3235a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3245a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 0 IbsLdOp: Load op */ 3255a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_LD_OP(x) ((x->ibs_op_data3_low & DC_MASK_LOAD_OP) != 0) 3265a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3275a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 1 IbsStOp: Store op */ 3285a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_ST_OP(x) ((x->ibs_op_data3_low & DC_MASK_STORE_OP) != 0) 3295a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3305a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 2 ibs_dc_l1_tlb_miss: Data cache L1TLB miss */ 3315a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_L1_TLB_MISS(x) ((x->ibs_op_data3_low & DC_MASK_L1_TLB_MISS) != 0) 3325a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3335a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 3 ibs_dc_l2_tlb_miss: Data cache L2TLB miss */ 3345a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_L2_TLB_MISS(x) ((x->ibs_op_data3_low & DC_MASK_L2_TLB_MISS) != 0) 3355a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3365a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 4 IbsDcL1tlbHit2M: Data cache L1TLB hit in 2M page */ 3375a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_L1_TLB_HIT_2MB(x) ((x->ibs_op_data3_low & DC_MASK_L1_HIT_2M) != 0) 3385a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3395a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 5 ibs_dc_l1_tlb_hit_1gb: Data cache L1TLB hit in 1G page */ 3405a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_L1_TLB_HIT_1GB(x) ((x->ibs_op_data3_low & DC_MASK_L1_HIT_1G) != 0) 3415a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3425a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 6 ibs_dc_l2_tlb_hit_2mb: Data cache L2TLB hit in 2M page */ 3435a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_L2_TLB_HIT_2MB(x) ((x->ibs_op_data3_low & DC_MASK_L2_HIT_2M) != 0) 3445a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3455a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 7 ibs_dc_miss: Data cache miss */ 3465a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_MISS(x) ((x->ibs_op_data3_low & DC_MASK_DC_MISS) != 0) 3475a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3485a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 8 ibs_dc_miss_acc: Misaligned access */ 3495a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_MISS_ACC(x) ((x->ibs_op_data3_low & DC_MASK_MISALIGN_ACCESS) != 0) 3505a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3515a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 9 ibs_dc_ld_bnk_con: Bank conflict on load operation */ 3525a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_LD_BNK_CON(x) ((x->ibs_op_data3_low & DC_MASK_LD_BANK_CONFLICT) != 0) 3535a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3545a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 10 ibs_dc_st_bnk_con: Bank conflict on store operation */ 3555a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_ST_BNK_CON(x) ((x->ibs_op_data3_low & DC_MASK_ST_BANK_CONFLICT) != 0) 3565a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3575a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 11 ibs_dc_st_to_ld_fwd : Data forwarded from store to load operation */ 3585a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_ST_TO_LD_FWD(x) ((x->ibs_op_data3_low & DC_MASK_ST_TO_LD_FOR) != 0) 3595a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3605a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 12 ibs_dc_st_to_ld_can: Data forwarding from store to load operation cancelled */ 3615a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_ST_TO_LD_CAN(x) ((x->ibs_op_data3_low & DC_MASK_ST_TO_LD_CANCEL) != 0) 3625a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3637a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown/** 13 ibs_dc_wc_mem_acc : WC memory access */ 3645a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_WC_MEM_ACC(x) ((x->ibs_op_data3_low & DC_MASK_WC_MEM_ACCESS) != 0) 3655a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3667a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown/** 14 ibs_dc_uc_mem_acc : UC memory access */ 3677a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown#define IBS_OP_IBS_DC_UC_MEM_ACC(x) ((x->ibs_op_data3_low & DC_MASK_UC_MEM_ACCESS) != 0) 3687a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 3695a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 15 ibs_locked_op: Locked operation */ 3705a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_LOCKED_OP(x) ((x->ibs_op_data3_low & DC_MASK_LOCKED_OP) != 0) 3715a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3725a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 16 ibs_dc_mab_hit : MAB hit */ 3735a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_MAB_HIT(x) ((x->ibs_op_data3_low & DC_MASK_MAB_HIT) != 0) 3745a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3755a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 17 IbsDcLinAddrValid: Data cache linear address valid */ 3765a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_LIN_ADDR_VALID(x) ((x->ibs_op_data3_low & DC_MASK_LIN_ADDR_VALID) != 0) 3775a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3785a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 18 ibs_dc_phy_addr_valid: Data cache physical address valid */ 3795a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_PHY_ADDR_VALID(x) ((x->ibs_op_data3_low & DC_MASK_PHY_ADDR_VALID) != 0) 3805a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3815a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 19 ibs_dc_l2_tlb_hit_1gb: Data cache L2TLB hit in 1G page */ 3825a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define IBS_OP_IBS_DC_L2_TLB_HIT_1GB(x) ((x->ibs_op_data3_low & DC_MASK_L2_HIT_1G) != 0) 3835a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3845a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3855a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 3865a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * Aggregate the IBS derived event. Increase the 3875a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * derived event count by one. 3885a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 3895a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define AGG_IBS_EVENT(EV) opd_log_ibs_event(EV, trans) 3905a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3915a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng/** 3925a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * Aggregate the IBS latency/cycle counts. Increase the 3935a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng * derived event count by the specified count value. 3945a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng */ 3955a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#define AGG_IBS_COUNT(EV, COUNT) opd_log_ibs_count(EV, trans, COUNT) 3965a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng 3975a4eb4eb367eccd4b976d1feae96cea96d2c50f2Ben Cheng#endif /*OPD_IBS_MACRO_H*/ 398