Lines Matching refs:regs

119    REGISTERS regs;

121    regs.d.eax = DPMIAPI_POST_WINDOWS_ORD << 16 | MGENVXD_DEVICE_ID;

122    regs.d.ebx = 0;

123    regs.d.ecx = 0;

124    int386(CHUNNEL_INT, &regs, &regs);

130    REGISTERS regs;

132    regs.d.eax = MGENVXD_WAIT_ORD << 16 | MGENVXD_DEVICE_ID;

133    int386(CHUNNEL_INT, &regs, &regs);

134    return regs.d.eax;

139    REGISTERS   regs;

141    regs.d.eax = MGENVXD_GETQUEUECTR_ORD << 16 | MGENVXD_DEVICE_ID;

142    regs.d.ebx = qNo;

143    int386(CHUNNEL_INT, &regs, &regs);

145    return regs.d.eax;

150    REGISTERS   regs;

152    regs.d.eax = MGENVXD_MOVENODE_ORD << 16 | MGENVXD_DEVICE_ID;

153    regs.d.ebx = qFrom;

154    regs.d.ecx = qTo;

155    int386(CHUNNEL_INT, &regs, &regs);

157    return (RTQ_NODE *) regs.d.eax;

162    REGISTERS   regs;

164    regs.d.eax = MGENVXD_GETNODE_ORD << 16 | MGENVXD_DEVICE_ID;

165    regs.d.ebx = q;

166    int386(CHUNNEL_INT, &regs, &regs);

168    return (RTQ_NODE *) regs.d.eax;

173    REGISTERS   regs;

175    regs.d.eax = MGENVXD_MASTERNODE_ORD << 16 | MGENVXD_DEVICE_ID;

176    int386(CHUNNEL_INT, &regs, &regs);

177    *size = regs.d.ecx;

179    return (RTQ_NODE *) regs.d.eax;

184    REGISTERS   regs;

186    regs.d.eax = MGENVXD_FLUSHNODE_ORD << 16 | MGENVXD_DEVICE_ID;

187    regs.d.ebx = qFrom;

188    regs.d.ecx = qTo;

189    int386(CHUNNEL_INT, &regs, &regs);

191    return (RTQ_NODE *) regs.d.eax;

196    REGISTERS   regs;

198    regs.d.eax = MGENVXD_MCOUNT_ORD << 16 | MGENVXD_DEVICE_ID;

199    regs.d.ebx = lowerOrderBits;

200    regs.d.ecx = upperOrderBits;

201    int386(CHUNNEL_INT, &regs, &regs);

203    return regs.d.eax;

208    REGISTERS   regs;

210    regs.d.eax = MGENVXD_SANITYCHECK_ORD << 16 | MGENVXD_DEVICE_ID;

211    int386(CHUNNEL_INT, &regs, &regs);

213    return regs.d.eax;

218    REGISTERS   regs;

220    regs.d.eax = MGENVXD_WAKEUPDLL_ORD << 16 | MGENVXD_DEVICE_ID;

221    int386(CHUNNEL_INT, &regs, &regs);