Lines Matching refs:srcStep
47 srcStep RN 1
104 M_LDR ValC, [pSrc], srcStep ;// Load [c3 c2 c1 c0]
105 M_LDR ValD, [pSrc], srcStep ;// Load [d3 d2 d1 d0]
106 M_LDR ValE, [pSrc], srcStep ;// Load [e3 e2 e1 e0]
107 SUB pSrc, pSrc, srcStep, LSL #2
119 LDR ValD, [pSrc, srcStep, LSL #1] ;// Load [d3 d2 d1 d0]
126 LDR ValF, [pSrc, srcStep, LSL #2] ;// Load [f3 f2 f1 f0]
127 M_LDR ValB, [pSrc], srcStep ;// Load [b3 b2 b1 b0]
134 SUB ValA, pSrc, srcStep, LSL #1
147 LDR ValG, [pSrc, srcStep, LSL #2] ;// Load [g3 g2 g1 g0]
172 ADD pSrc, pSrc, srcStep, LSL #1
178 SUB pSrc, pSrc, srcStep, LSL #2