| /external/llvm/lib/MC/ |
| H A D | MCCodeGenInfo.cpp | 18 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, argument
20 RelocationModel = RM;
|
| /external/libpng/contrib/pngminim/decoder/ |
| H A D | makefile | 8 RM=rm -f macro
40 $(RM) pngm2pnm$(O)
41 $(RM) pngm2pnm$(E)
42 $(RM) $(OBJS)
|
| /external/libpng/contrib/pngminim/encoder/ |
| H A D | makefile | 8 RM=rm -f macro
39 $(RM) pnm2pngm$(O)
40 $(RM) pnm2pngm$(E)
41 $(RM) $(OBJS)
|
| /external/libpng/contrib/pngminim/preader/ |
| H A D | makefile | 8 RM=rm -f macro
56 $(RM) rpng2-x$(O)
57 $(RM) rpng2-x$(E)
58 $(RM) $(OBJS)
|
| /external/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 27 Reloc::Model RM, CodeModel::Model CM,
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.cpp | 29 Reloc::Model RM) :
60 UseSmallSection = !IsLinux && (RM == Reloc::Static);
27 MipsSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool little, Reloc::Model RM) argument
|
| H A D | MipsTargetMachine.cpp | 41 Reloc::Model RM, CodeModel::Model CM,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, isLittle, RM),
64 Reloc::Model RM, CodeModel::Model CM,
66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
73 Reloc::Model RM, CodeModel::Model CM,
75 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
39 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
62 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
71 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 54 static MCCodeGenInfo *createNVPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
58 X->InitMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCTargetDesc.cpp | 53 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
57 X->InitMCCodeGenInfo(RM, CM, OL);
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | BuiltinFunctionChecker.cpp | 56 MemRegionManager& RM = C.getStoreManager().getRegionManager(); local
58 RM.getAllocaRegion(CE, C.blockCount(), C.getLocationContext());
|
| /external/llvm/lib/Target/CellSPU/MCTargetDesc/ |
| H A D | SPUMCTargetDesc.cpp | 65 static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 66 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
|
| /external/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeTargetMachine.cpp | 37 Reloc::Model RM, CodeModel::Model CM,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 32 Reloc::Model RM, CodeModel::Model CM,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| H A D | XCoreMCTargetDesc.cpp | 64 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
68 X->InitMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 26 Reloc::Model RM, CodeModel::Model CM,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 43 Reloc::Model RM, CodeModel::Model CM,
45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 Reloc::Model RM, CodeModel::Model CM,
61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
85 Reloc::Model RM, CodeModel::Model CM,
87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/CellSPU/ |
| H A D | SPUTargetMachine.cpp | 37 Reloc::Model RM, CodeModel::Model CM,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 67 Reloc::Model RM,
70 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
64 HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 53 static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
57 X->InitMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 68 Reloc::Model RM,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
86 Reloc::Model RM, CodeModel::Model CM,
88 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
96 Reloc::Model RM, CodeModel::Model CM,
98 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 38 Reloc::Model RM, CodeModel::Model CM,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
58 Reloc::Model RM, CodeModel::Model CM,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
68 Reloc::Model RM, CodeModel::Model CM,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 31 Reloc::Model RM, CodeModel::Model CM,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
82 Reloc::Model RM,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
94 Reloc::Model RM,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 68 Reloc::Model RM, CodeModel::Model CM,
71 CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
65 LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| H A D | MBlazeMCTargetDesc.cpp | 64 static MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM, argument
68 if (RM == Reloc::Default)
69 RM = Reloc::Static;
72 X->InitMCCodeGenInfo(RM, CM, OL);
|