/external/llvm/include/llvm/Transforms/Utils/ |
H A D | AddrModeMatcher.h | 50 static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) { argument 51 AM.print(OS); 75 Instruction *MI, ExtAddrMode &AM) 76 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) { 73 AddressingModeMatcher(SmallVectorImpl<Instruction*> &AMI, const TargetLowering &T, Type *AT, Instruction *MI, ExtAddrMode &AM) argument
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/external/llvm/lib/Analysis/ |
H A D | TypeBasedAliasAnalysis.cpp | 220 const MDNode *AM = LocA.TBAATag; local 221 if (!AM) return AliasAnalysis::alias(LocA, LocB); 226 if (Aliases(AM, BM))
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 319 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { argument 320 switch (AM) { 458 const char *AM = getIndexedModeName(LD->getAddressingMode()); local 459 if (*AM) 460 OS << ", " << AM; local 469 const char *AM = getIndexedModeName(ST->getAddressingMode()); local 470 if (*AM) 471 OS << ", " << AM; local
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H A D | TargetLowering.cpp | 3257 /// by AM is legal for this target, for a load/store of the specified type. 3258 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 3264 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3268 if (AM.BaseGV) 3272 switch (AM.Scale) { 3276 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3281 if (AM.HasBaseReg || AM [all...] |
H A D | DAGCombiner.cpp | 6733 TargetLowering::AddrMode AM; 6738 AM.BaseOffs = Offset->getSExtValue(); 6741 AM.Scale = 1; 6746 AM.BaseOffs = -Offset->getSExtValue(); 6749 AM.Scale = 1; 6753 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6799 ISD::MemIndexedMode AM = ISD::UNINDEXED; local 6800 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6854 BasePtr, Offset, AM); 6857 BasePtr, Offset, AM); 6929 ISD::MemIndexedMode AM = ISD::UNINDEXED; local [all...] |
H A D | SelectionDAG.cpp | 526 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, argument 530 assert((AM & 7) == AM && 531 "AM may not require more than 3 bits!"); 533 (AM << 2) | 4242 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument 4271 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); 4275 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument 4296 bool Indexed = AM != ISD::UNINDEXED; 4306 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MM 4348 getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) argument 4481 getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); 107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); 108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); 139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { argument 142 if (AM.hasSymbolicDisplacement()) 148 AM.GV = G->getGlobal(); 149 AM.Disp += G->getOffset(); 150 //AM.SymbolFlags = G->getTargetFlags(); 152 AM.CP = CP->getConstVal(); 153 AM 171 MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) argument 184 MatchAddress(SDValue N, MSP430ISelAddressMode &AM) argument 250 MSP430ISelAddressMode AM; local 303 ISD::MemIndexedMode AM = LD->getAddressingMode(); local [all...] |
H A D | MSP430ISelLowering.cpp | 940 ISD::MemIndexedMode &AM, 962 AM = ISD::POST_INC; 937 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 123 const X86AddressMode &AM) { 124 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8); 126 if (AM.BaseType == X86AddressMode::RegBase) 127 MIB.addReg(AM.Base.Reg); 129 assert(AM.BaseType == X86AddressMode::FrameIndexBase); 130 MIB.addFrameIndex(AM.Base.FrameIndex); 133 MIB.addImm(AM 122 addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) argument [all...] |
H A D | X86FastISel.cpp | 83 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 85 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM); 86 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM); 91 bool X86SelectAddress(const Value *V, X86AddressMode &AM); 92 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM); 178 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, argument 228 DL, TII.get(Opc), ResultReg), AM); 237 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { argument 278 DL, TII.get(Opc)), AM).addReg(Val); 283 const X86AddressMode &AM) { 282 X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM) argument 339 X86SelectAddress(const Value *V, X86AddressMode &AM) argument 599 X86SelectCallAddress(const Value *V, X86AddressMode &AM) argument 1436 X86AddressMode AM; local 1443 X86AddressMode AM; local 1773 X86AddressMode AM; local 2070 X86AddressMode AM; local 2185 X86AddressMode AM; local [all...] |
H A D | X86ISelDAGToDAG.cpp | 197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM); 198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM); 199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM); 201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 232 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, argument 235 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 236 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) : 237 AM 568 FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM) argument 587 MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM) argument 615 MatchWrapper(SDValue N, X86ISelAddressMode &AM) argument 702 MatchAddress(SDValue N, X86ISelAddressMode &AM) argument 747 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 790 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 857 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 938 MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, unsigned Depth) argument 1249 MatchAddressBase(SDValue N, X86ISelAddressMode &AM) argument 1279 X86ISelAddressMode AM; local 1364 X86ISelAddressMode AM; local 1428 X86ISelAddressMode AM; local [all...] |
H A D | X86InstrInfo.cpp | 3511 X86AddressMode AM; local 3512 AM.BaseType = X86AddressMode::FrameIndexBase; 3513 AM.Base.FrameIndex = FrameIx; 3515 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
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/external/chromium/chrome/common/extensions/docs/examples/extensions/benchmark/jquery/ |
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/external/icu4c/i18n/unicode/ |
H A D | calendar.h | 257 AM, enumerator in enum:Calendar::EAmpm
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 583 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 586 if (AM != ISD::UNINDEXED) { 722 ISD::MemIndexedMode AM = ST->getAddressingMode(); local 725 if (AM != ISD::UNINDEXED) {
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H A D | HexagonISelLowering.cpp | 632 ISD::MemIndexedMode &AM, 657 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1552 /// AM is legal for this target, for a load/store of the specified type. 1553 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1556 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 1561 if (AM.BaseGV) { 1565 int Scale = AM.Scale; 629 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1198 /// by AM is legal for this target, for a load/store of the specified type. 1203 NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1215 if (AM.BaseGV) { 1216 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale) 1221 switch (AM.Scale) { 1225 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 720 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 723 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 756 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 759 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 776 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 779 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 849 ISD::MemIndexedMode AM local 935 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); local 1251 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 1324 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 1397 ISD::MemIndexedMode AM = LD->getAddressingMode(); local [all...] |
H A D | ARMISelLowering.cpp | 9176 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, argument 9178 int Scale = AM.Scale; 9195 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 9210 /// by AM is legal for this target, for a load/store of the specified type. 9211 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 9214 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 9218 if (AM.BaseGV) 9221 switch (AM.Scale) { 9230 if (AM.BaseOffs) 9237 return isLegalT2ScaledAddressingMode(AM, V 9387 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument 9425 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1566 /// by AM is legal for this target, for a load/store of the specified type. 1568 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1571 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1575 if (AM.BaseGV) { 1576 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1577 AM.BaseOffs%4 == 0; 1583 if (AM [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 611 static const char* getIndexedModeName(ISD::MemIndexedMode AM); 1610 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, 1613 SubclassData |= AM << 2; 1614 assert(getAddressingMode() == AM && "MemIndexedMode encoding error!"); 1648 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, 1651 VTs, AM, MemVT, MMO) { 1679 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, 1682 VTs, AM, MemVT, MMO) { 1609 LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument 1647 LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument 1678 StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 3250 SPUTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 3254 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0) 3258 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs)) 3262 if (AM [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenDAGPatterns.cpp | 706 const ComplexPattern *AM = P->getComplexPatternInfo(CGP); local 707 if (AM) 708 Size += AM->getNumOperands() * 3;
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 226 /// AM - This is used to represent complex addressing, as well as other kinds 228 TargetLowering::AddrMode AM; member in struct:__anon9697::Formula 231 /// non-empty, AM.HasBaseReg should be set to true. 235 /// when AM.Scale is not zero. 329 AM.HasBaseReg = true; 335 AM.HasBaseReg = true; 351 AM.BaseGV ? AM.BaseGV->getType() : 384 if (AM.BaseGV) { 386 WriteAsOperand(OS, AM 1272 isLegalUse(const TargetLowering::AddrMode &AM, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument 1329 isLegalUse(TargetLowering::AddrMode AM, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument 2023 TargetLowering::AddrMode AM; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1114 ISD::MemIndexedMode &AM, 1135 AM = ISD::PRE_INC; 1159 AM = ISD::PRE_INC; 5818 // by AM is legal for this target, for a load/store of the specified type. 5819 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 5824 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5828 if (AM.BaseGV) 5832 switch (AM.Scale) { 5836 if (AM 1112 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument [all...] |