/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { argument 20 switch (Opcode) {
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument 24 switch (Opcode) {
|
H A D | ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode(); local 27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
H A D | MLxExpansionPass.cpp | 144 unsigned Opcode = MCID.getOpcode(); local 145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsDirectObjLower.cpp | 58 int Opcode = InstIn.getOpcode(); local 60 if (Opcode == Mips::DEXT) 77 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); 83 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 90 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, argument 94 const MCInstrDesc &MCID = TII.get(Opcode); 145 unsigned Opcode = MI->getOpcode(); local 148 GetInstrType(Opcode, isFirst, isSingle, isCracked, 182 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4)) 203 unsigned Opcode = MI->getOpcode(); local 206 GetInstrType(Opcode, isFirst, isSingle, isCracked, 211 if (Opcode == PPC::MTCTR || Opcode [all...] |
/external/webkit/Source/JavaScriptCore/bytecode/ |
H A D | Opcode.h | 220 typedef void* Opcode; typedef in namespace:JSC 222 typedef const void* Opcode; typedef in namespace:JSC 225 typedef OpcodeID Opcode; typedef in namespace:JSC
|
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelDAGToDAG.cpp | 190 unsigned Opcode = Node->getOpcode(); local 201 switch (Opcode) {
|
/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeMCCodeEmitter.cpp | 180 unsigned Opcode = MI.getOpcode(); local 181 const MCInstrDesc &Desc = MCII.get(Opcode);
|
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; local 166 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; local 175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
H A D | SparcInstrInfo.cpp | 177 unsigned Opcode = I->getOpcode(); local 178 if (Opcode != SP::BCOND && Opcode != SP::FBCOND) 179 return true; //Unknown Opcode 205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
|
/external/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.h | 46 uint8_t Opcode; member in class:llvm::X86Disassembler::RecognizableInstr
|
/external/webkit/Source/WebCore/xml/ |
H A D | XPathPredicate.h | 67 enum Opcode { enum in class:WebCore::XPath::NumericOp 70 NumericOp(Opcode, Expression* lhs, Expression* rhs); 75 Opcode m_opcode; 80 enum Opcode { OP_EQ, OP_NE, OP_GT, OP_LT, OP_GE, OP_LE }; enum in class:WebCore::XPath::EqTestOp 81 EqTestOp(Opcode, Expression* lhs, Expression* rhs); 87 Opcode m_opcode; 92 enum Opcode { OP_And, OP_Or }; enum in class:WebCore::XPath::LogicalOp 93 LogicalOp(Opcode, Expression* lhs, Expression* rhs); 99 Opcode m_opcode;
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 336 unsigned Opcode = 0; local 339 Opcode = MSP430::MOV8rm_POST; 342 Opcode = MSP430::MOV16rm_POST; 348 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
|
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 120 unsigned Opcode = MI.getOpcode(); local 121 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
|
/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 236 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { argument 252 Inst.setOpcode(Opcode); 258 unsigned Opcode) { 303 Inst.setOpcode(Opcode); 396 unsigned Opcode = OutMI.getOpcode(); local 399 OutMI.setOpcode(Opcode); 415 unsigned Opcode; local 418 case X86::TAILJMPr: Opcode = X86::JMP32r; break; 420 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; 425 OutMI.setOpcode(Opcode); 257 SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; local 55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) 69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; local 70 BuildMI(MBB, I, dl, TII.get(Opcode)) 125 int Opcode; local 127 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; 132 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; 134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); 262 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; local 263 BuildMI(MBB, MBBI, dl, TII.get(Opcode)) 266 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; local [all...] |
H A D | XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode(); local 59 if (Opcode == XCore::LDWFI) 80 int Opcode = MI->getOpcode(); local 81 if (Opcode == XCore::STWFI)
|
H A D | XCoreRegisterInfo.cpp | 138 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; local 139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) 143 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; local 144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) 245 llvm_unreachable("Unexpected Opcode"); 266 llvm_unreachable("Unexpected Opcode"); 294 llvm_unreachable("Unexpected Opcode"); 309 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; local 310 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
/external/llvm/lib/Transforms/Utils/ |
H A D | AddrModeMatcher.cpp | 155 bool AddressingModeMatcher::MatchOperationAddr(User *AddrInst, unsigned Opcode, argument 160 switch (Opcode) { 212 if (Opcode == Instruction::Shl)
|
H A D | BypassSlowDivision.cpp | 231 unsigned Opcode = J->getOpcode(); local 232 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv; 233 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem; 234 bool UseSignedOp = Opcode == Instruction::SDiv || 235 Opcode == Instruction::SRem;
|
/external/llvm/lib/VMCore/ |
H A D | Instruction.cpp | 382 bool Instruction::isAssociative(unsigned Opcode) { argument 383 return Opcode == And || Opcode == Or || Opcode == Xor || 384 Opcode == Add || Opcode == Mul; 415 bool Instruction::isIdempotent(unsigned Opcode) { argument 416 return Opcode == And || Opcode == Or; 428 bool Instruction::isNilpotent(unsigned Opcode) { argument [all...] |
/external/llvm/include/llvm/ |
H A D | Instruction.h | 96 static inline bool isBinaryOp(unsigned Opcode) { argument 97 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd; 100 /// @brief Determine if the Opcode is one of the shift instructions. 101 static inline bool isShift(unsigned Opcode) { argument 102 return Opcode >= Shl && Opcode <= AShr;
|
/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 151 unsigned Opcode; member in class:llvm::MCInst 155 MCInst() : Opcode(0) {} 157 void setOpcode(unsigned Op) { Opcode = Op; } 158 unsigned getOpcode() const { return Opcode; }
|
/external/llvm/lib/CodeGen/ |
H A D | MachineSSAUpdater.cpp | 112 MachineInstr *InsertNewDef(unsigned Opcode, argument 118 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
|