Searched defs:SReg (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/CodeGen/
H A DVirtRegMap.h137 /// @brief records virtReg is a split live interval from SReg.
138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { argument
139 Virt2SplitMap[virtReg] = SReg;
H A DRegisterScavenging.cpp352 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); local
355 if (!isAliasUsed(SReg)) {
356 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
357 return SReg;
364 ScavengedReg = SReg;
368 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
372 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
377 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
385 // ScavengedReg = SReg;
388 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp589 unsigned SReg; local
593 SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj);
595 SReg = is64Bit ? PPC::X0 : PPC::R0;
598 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
600 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
601 .addReg(SReg, RegState::Kill)
622 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp238 unsigned SReg = Reg - ARM::S0; local
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
245 OutStreamer.AddComment(Twine(SReg));
H A DARMBaseInstrInfo.cpp3383 unsigned SReg, unsigned &Lane) {
3384 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3391 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
3382 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument

Completed in 93 milliseconds