/external/clang/test/Preprocessor/ |
H A D | macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__ macro 33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macro}} variable
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/external/clang/test/Parser/ |
H A D | cxx-using-declaration.cpp | 4 int VA; member in namespace:A 9 using A::VA; 15 VA = 1;
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/external/clang/test/CXX/special/class.dtor/ |
H A D | p3-0x.cpp | 140 struct VA { struct 142 virtual ~VA() {} 145 struct VB : VA 149 struct TVB : VA
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/external/mksh/src/ |
H A D | shf.c | 771 #define VA(type) va_arg(args, type) macro 820 tmp = VA(int); 877 lnum = (long)VA(ssize_t); 879 lnum = VA(long); 881 lnum = (long)(short)VA(int); 883 lnum = (long)VA(int); 890 lnum = VA(size_t); 892 lnum = VA(unsigned long); 894 lnum = (unsigned long)(unsigned short)VA(int); 896 lnum = (unsigned long)VA(unsigne [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombinePHI.cpp | 880 Value *VA = PN.getIncomingValue(i); local 886 PN.setIncomingValue(j, VA);
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 727 CCValAssign &VA = ArgLocs[i]; local 728 MVT RegVT = VA.getLocVT(); 732 switch (VA.getLocInfo()) { 748 if (VA.isRegLoc()) { 749 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 752 assert(VA.isMemLoc()); 760 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; 761 unsigned StackLoc = VA.getLocMemOffset() + 4; 899 CCValAssign &VA = ArgLocs[i]; local 902 if (VA 1042 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 324 CCValAssign &VA = ArgLocs[i]; local 325 if (VA.isRegLoc()) { 327 EVT RegVT = VA.getLocVT(); 339 RegInfo.addLiveIn(VA.getLocReg(), VReg); 345 if (VA.getLocInfo() == CCValAssign::SExt) 347 DAG.getValueType(VA.getValVT())); 348 else if (VA.getLocInfo() == CCValAssign::ZExt) 350 DAG.getValueType(VA.getValVT())); 352 if (VA.getLocInfo() != CCValAssign::Full) 353 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA 415 CCValAssign &VA = RVLocs[i]; local 468 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 110 CCValAssign &VA = RVLocs[i]; local 111 assert(VA.isRegLoc() && "Can only return in registers!"); 113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 169 CCValAssign &VA = ArgLocs[i]; local 182 if (VA.isRegLoc()) { 183 if (VA.needsCustom()) { 184 assert(VA.getLocVT() == MVT::f64); 186 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 214 if (VA 411 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1886 CCValAssign &VA = ArgLocs[i]; local 1887 MVT ArgVT = ArgVTs[VA.getValNo()]; 1894 if (VA.isRegLoc() && !VA.needsCustom()) { 1896 } else if (VA.needsCustom()) { 1898 if (VA.getLocVT() != MVT::f64 || 1900 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1936 CCValAssign &VA = ArgLocs[i]; local 1937 unsigned Arg = ArgRegs[VA.getValNo()]; 1938 MVT ArgVT = ArgVTs[VA [all...] |
H A D | ARMISelLowering.cpp | 1196 CCValAssign VA = RVLocs[i]; local 1199 if (VA.needsCustom()) { 1201 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1205 VA = RVLocs[++i]; // skip ahead to next loc 1206 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1212 if (VA.getLocVT() == MVT::v2f64) { 1217 VA = RVLocs[++i]; // skip ahead to next loc 1218 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1221 VA = RVLocs[++i]; // skip ahead to next loc 1222 Hi = DAG.getCopyFromReg(Chain, dl, VA 1252 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 1265 PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVector<SDValue, 8> &MemOpChains, ISD::ArgFlagsTy Flags) const argument 1357 CCValAssign &VA = ArgLocs[i]; local 1827 CCValAssign &VA = ArgLocs[i]; local 1892 CCValAssign &VA = RVLocs[i]; local 2473 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, DebugLoc dl) const argument 2615 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 318 CCValAssign &VA = RVLocs[i]; local 320 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 425 CCValAssign &VA = ArgLocs[i]; local 426 if (VA.isMemLoc()) { 449 CCValAssign &VA = ArgLocs[i]; local 454 switch (VA.getLocInfo()) { 461 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 464 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 467 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 471 if (VA 834 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 760 CCValAssign &VA = ValLocs[0]; 763 if (VA.getLocInfo() != CCValAssign::Full) 766 if (!VA.isRegLoc()) 771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 774 unsigned SrcReg = Reg + VA.getValNo(); 776 EVT DstVT = VA.getValVT(); 800 unsigned DstReg = VA.getLocReg(); 809 MRI.addLiveOut(VA.getLocReg()); 1708 CCValAssign &VA local [all...] |
H A D | X86ISelLowering.cpp | 1515 CCValAssign &VA = RVLocs[i]; local 1516 assert(VA.isRegLoc() && "Can only return in registers!"); 1521 if (VA.getLocInfo() == CCValAssign::SExt) 1522 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1523 else if (VA.getLocInfo() == CCValAssign::ZExt) 1524 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1525 else if (VA.getLocInfo() == CCValAssign::AExt) 1526 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1527 else if (VA.getLocInfo() == CCValAssign::BCvt) 1528 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA 1672 CCValAssign &VA = RVLocs[i]; local 1802 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument 1883 CCValAssign &VA = ArgLocs[i]; local 2118 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2265 CCValAssign &VA = ArgLocs[i]; local 2395 CCValAssign &VA = ArgLocs[i]; local 2792 CCValAssign &VA = RVLocs[i]; local 2855 CCValAssign &VA = ArgLocs[i]; local 2878 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 941 CCValAssign &VA = ArgLocs[i]; local 945 switch (VA.getLocInfo()) { 949 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 952 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 955 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 961 if (VA.isRegLoc()) { 962 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 964 assert(VA.isMemLoc()); 966 int Offset = VA.getLocMemOffset(); 1115 CCValAssign &VA local 1246 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/webkit/Source/WebKit/android/content/ |
H A D | address_detector.cpp | 722 VA = 52, // VA Virginia enumerator in enum:USState 753 DC, VA, DC, DC, DC, DC, MD, MD, MD, MD, // 200-209 755 VA, VA, VA, VA, VA, VA, VA, V [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 1147 CCValAssign &VA = ArgLocs[ArgNo]; local 1149 if (VA.isRegLoc()) { 1188 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1317 CCValAssign &VA = ArgLocs[ArgRegIdx]; local 1340 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1457 CCValAssign VA = RVLocs[i]; local 1459 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1492 CCValAssign &VA = RVLocs[i]; local 1493 assert(VA [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2423 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2425 unsigned LocMemOffset = VA.getLocMemOffset(); 2514 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2518 bool IsRegLoc = VA.isRegLoc(); 2524 LocMemOffset = VA.getLocMemOffset(); 2527 VA.getLocReg()); 2667 CCValAssign &VA = ArgLocs[i]; local 2668 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2677 MFI, DAG, Arg, VA, Flag 2419 WriteByValArg(SDValue Chain, DebugLoc dl, SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, MVT PtrType, bool isLittle) argument 2510 PassByValArg64(SDValue Chain, DebugLoc dl, SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, EVT PtrTy, bool isLittle) argument 2907 ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, std::vector<SDValue> &OutChains, SelectionDAG &DAG, unsigned NumWords, SDValue FIN, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, const Argument *FuncArg) argument 2934 CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, MachineFrameInfo *MFI, bool IsRegLoc, SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, EVT PtrTy, const Argument *FuncArg) argument 3007 CCValAssign &VA = ArgLocs[i]; local 3200 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1787 CCValAssign &VA = ArgLocs[i]; local 1790 if (VA.isRegLoc()) { 1792 EVT ValVT = VA.getValVT(); 1815 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1821 assert(VA.isMemLoc()); 1823 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1824 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1829 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2825 CCValAssign &VA = RVLocs[i]; local 2826 EVT VT = VA 3088 CCValAssign &VA = ArgLocs[i]; local 3589 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/qemu/ |
H A D | ppc-dis.c | 820 /* The VA field in a VA, VX or VXR form instruction. */ 821 #define VA UI + 1 824 /* The VB field in a VA, VX or VXR form instruction. */ 825 #define VB VA + 1 828 /* The VC field in a VA form instruction. */ 832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 846 /* The SHB field in a VA form instruction. */ 1723 /* An VA form instruction. */ 1726 /* The mask for an VA for 817 #define VA macro [all...] |