Searched defs:requiresRegisterScavenging (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/Target/CellSPU/
H A DSPURegisterInfo.h63 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const function in class:llvm::SPURegisterInfo
/external/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h70 /// requiresRegisterScavenging - returns true since we may need scavenging for
72 bool requiresRegisterScavenging(const MachineFunction &MF) const { function in struct:llvm::HexagonRegisterInfo
/external/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp142 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { function in class:MipsRegisterInfo
/external/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp87 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { function in class:XCoreRegisterInfo
96 return requiresRegisterScavenging(MF);
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp64 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { function in class:PPCRegisterInfo
94 return requiresRegisterScavenging(MF);
317 if (requiresRegisterScavenging(MF))
327 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
344 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
526 if (requiresRegisterScavenging(MF)) {
590 if (requiresRegisterScavenging(MF)) {
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h629 /// requiresRegisterScavenging - returns true if the target requires (and can
631 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { function in class:llvm::TargetRegisterInfo
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp725 requiresRegisterScavenging(const MachineFunction &MF) const { function in class:ARMBaseRegisterInfo

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