Searched defs:scale (Results 1 - 10 of 10) sorted by relevance

/dalvik/vm/compiler/codegen/x86/libenc/
H A Ddec_base.cpp469 unsigned scale = 0; local
489 // scale = sib.scale == 0 ? 0 : (1<<sib.scale);
490 scale = (1<<sib.scale);
537 opnd = EncoderBase::Operand(opndDesc.size, base, index, scale, disp);
H A Denc_wrapper.cpp58 inline void add_m_scale(EncoderBase::Operands & args, int baseReg, int indexReg, int scale, argument
62 map_of_regno_2_regname[indexReg], scale,
65 inline void add_m_disp_scale(EncoderBase::Operands & args, int baseReg, int disp, int indexReg, int scale, argument
69 map_of_regno_2_regname[indexReg], scale,
94 if(opnd.scale() != 0) {
98 getRegNameString(opnd.index()), opnd.scale());
257 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale,
261 add_m_scale(args, base_reg, index_reg, scale, size);
272 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale,
275 add_m_scale(args, base_reg, index_reg, scale, siz
256 encoder_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
270 encoder_reg_mem_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type, char * stream) argument
285 encoder_mem_disp_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
299 encoder_movzs_mem_disp_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type, char * stream) argument
314 encoder_reg_mem_disp_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type, char* stream) argument
[all...]
H A Denc_prvt.h265 * @brief Describes SIB (scale,index,base) byte.
270 unsigned char scale:2; member in struct:SIB
H A Dencoder.h333 // Can also serve as a full memory operand with base,index, displacement and scale.
349 M_Opnd(I_32 disp, Reg_No rbase, Reg_No rindex, unsigned scale): argument
350 RM_Opnd(Mem), m_disp(disp), m_scale(scale), m_index(rindex), m_base(rbase) {}
358 inline const Imm_Opnd & scale(void) const { return m_scale; } function in class:M_Opnd
382 M_Index_Opnd(Reg_No base, Reg_No index, I_32 disp, unsigned scale): argument
383 M_Opnd(disp, base, index, scale) {}
/dalvik/vm/compiler/codegen/arm/Thumb/
H A DFactory.cpp470 int rIndex, int rDest, int scale, OpSize size)
476 if (scale) {
479 first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
506 if (scale)
513 int rIndex, int rSrc, int scale, OpSize size)
519 if (scale) {
521 first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
544 if (scale)
469 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
512 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
/dalvik/vm/compiler/codegen/mips/Mips32/
H A DFactory.cpp422 int rIndex, int rDest, int scale, OpSize size)
440 if (!scale) {
443 first = opRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
484 int rIndex, int rSrc, int scale, OpSize size)
503 if (!scale) {
506 first = opRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
421 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
483 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
/dalvik/vm/compiler/codegen/arm/Thumb2/
H A DFactory.cpp714 int rIndex, int rDest, int scale, OpSize size)
719 bool thumbForm = (allLowRegs && (scale == 0));
735 if (scale) {
737 encodeShift(kArmLsl, scale));
768 load = newLIR4(cUnit, opcode, rDest, rBase, rIndex, scale);
778 int rIndex, int rSrc, int scale, OpSize size)
783 bool thumbForm = (allLowRegs && (scale == 0));
799 if (scale) {
801 encodeShift(kArmLsl, scale));
828 store = newLIR4(cUnit, opcode, rSrc, rBase, rIndex, scale);
713 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
777 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
[all...]
/dalvik/vm/compiler/codegen/arm/
H A DCodegenDriver.cpp407 RegLocation rlDest, int scale)
441 if (scale) {
443 opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
462 scale, size);
476 RegLocation rlSrc, int scale)
519 if (scale) {
521 opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
539 scale, size);
551 RegLocation rlSrc, int scale)
622 scale, kWor
405 genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size, RegLocation rlArray, RegLocation rlIndex, RegLocation rlDest, int scale) argument
474 genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size, RegLocation rlArray, RegLocation rlIndex, RegLocation rlSrc, int scale) argument
549 genArrayObjectPut(CompilationUnit *cUnit, MIR *mir, RegLocation rlArray, RegLocation rlIndex, RegLocation rlSrc, int scale) argument
[all...]
/dalvik/vm/compiler/codegen/mips/
H A DCodegenDriver.cpp473 RegLocation rlDest, int scale)
494 if (scale) {
495 opRegRegImm(cUnit, kOpLsl, regPtr, rlIndex.lowReg, scale);
507 if (scale) {
537 RegLocation rlSrc, int scale)
565 if (scale) {
566 opRegRegImm(cUnit, kOpLsl, tReg, rlIndex.lowReg, scale);
579 if (scale) {
609 RegLocation rlSrc, int scale)
683 scale, kWor
471 genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size, RegLocation rlArray, RegLocation rlIndex, RegLocation rlDest, int scale) argument
535 genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size, RegLocation rlArray, RegLocation rlIndex, RegLocation rlSrc, int scale) argument
607 genArrayObjectPut(CompilationUnit *cUnit, MIR *mir, RegLocation rlArray, RegLocation rlIndex, RegLocation rlSrc, int scale) argument
[all...]
/dalvik/vm/compiler/codegen/x86/
H A DLowerHelper.cpp137 void set_mem_opnd_scale(LowOpndMem* mem, int base, bool isPhysical, int disp, int index, bool indexPhysical, int scale) { argument
153 mem->m_scale.value = scale;
566 int scale, int reg, LowOpndRegType type) {
570 scale, reg, true, type, stream);
574 scale, reg, true, type, stream);
577 scale, reg, true, type, stream);
583 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale,
600 return lower_mem_scale_reg(m, size, baseAll, disp, indexAll, scale, regAll, type);
603 isIndexPhysical, scale, reg, isPhysical, type, stream);
611 int base_reg, int disp, int index_reg, int scale, LowOpndRegTyp
565 lower_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, int disp, int index_reg, int scale, int reg, LowOpndRegType type) argument
582 dump_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type) argument
610 lower_reg_mem_scale(Mnemonic m, OpndSize size, int reg, int base_reg, int disp, int index_reg, int scale, LowOpndRegType type) argument
621 dump_reg_mem_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type) argument
804 load_effective_addr_scale(int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1500 movez_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1508 moves_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1547 move_mem_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1554 move_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1564 move_reg_to_mem_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale) argument
1572 move_reg_to_mem_disp_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale) argument
[all...]

Completed in 135 milliseconds