| /dalvik/vm/mterp/armv5te/ |
| H A D | binop2addr.S | 26 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
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| H A D | binopLit8.S | 25 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
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| H A D | unopNarrower.S | 18 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
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| H A D | unopWide.S | 16 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
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| H A D | unopWider.S | 16 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
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| H A D | footer.S | 20 mov rPC, r1 @ restore Dalvik pc
38 mov rPC, r0 @ set up dalvik pc
49 mov r0,rPC @ pass our target PC
57 mov r0,rPC @ pass our target PC
89 mov r0,rPC @ pass our target PC
102 mov rPC, r1 @ restore Dalvik pc
119 mov rPC, r0
145 mov rPC, r0 @ set up dalvik pc
169 mov r0,rPC
173 mov r1, rPC
[all...] |
| /dalvik/vm/mterp/armv6t2/ |
| H A D | OP_IPUT_QUICK.S | 12 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
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| H A D | OP_IPUT_WIDE_QUICK.S | 12 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
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| H A D | binop2addr.S | 25 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
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| H A D | unopWide.S | 15 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
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| /dalvik/vm/mterp/mips/ |
| H A D | OP_CONST_WIDE.S | 12 FETCH_ADVANCE_INST(5) # advance rPC, load rINST
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| H A D | OP_IPUT_QUICK.S | 11 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
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| H A D | binopLit8.S | 25 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
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| H A D | unflopWide.S | 19 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
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| H A D | unflopWider.S | 18 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
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| H A D | unopNarrower.S | 22 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
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| /dalvik/vm/mterp/x86/ |
| H A D | bindivLit16.S | 12 movswl 2(rPC),%ecx # ecx<- ssssCCCC
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| H A D | OP_INVOKE_STATIC.S | 12 movzwl 2(rPC),%eax # eax<- BBBB
29 movzwl 2(rPC),%eax
53 movl rPC, OUT_ARG1(%esp)
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| H A D | OP_INVOKE_SUPER.S | 12 movzwl 2(rPC),%eax # eax<- BBBB
18 movzwl 4(rPC),rINST # rINST<- GFED or CCCC
53 movzwl 2(rPC),%ecx # ecx<- BBBB
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| H A D | footer.S | 27 * should be reached via a direct jump and rPC set beforehand.
35 * the interpreter and code cache. rPC must be set on entry.
40 movl rPC, OUT_ARG0(%esp)
55 * rPC <= Dalvik PC of this instruction
76 * chain to it. rPC must be set on entry.
82 movl %eax, rPC
84 movl rPC,OUT_ARG0(%esp)
103 * rPC set on entry.
110 movl %ebx, rPC
113 movl rPC,OUT_ARG
[all...] |
| H A D | OP_NEW_INSTANCE.S | 14 movzwl 2(rPC),%eax # eax<- BBBB
64 movl rPC, OUT_ARG1(%esp)
95 movzwl 2(rPC),%eax
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| /dalvik/vm/mterp/out/ |
| H A D | InterpAsm-mips.S | 26 s0 rPC interpreted program counter, used for fetching instructions
35 #define rPC s0 define
67 #define LOAD_PC_FROM_SELF() lw rPC, offThread_pc(rSELF)
68 #define SAVE_PC_TO_SELF() sw rPC, offThread_pc(rSELF)
79 sw rPC, (offStackSaveArea_currentPc - sizeofStackSaveArea)(rFP)
84 #define FETCH_INST() lhu rINST, (rPC)
86 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \
87 addu rPC, rPC, ((_count) * 2)
93 #define FETCH_ADVANCE_INST_RB(rd) addu rPC, rP
[all...] |
| H A D | InterpAsm-armv5te.S | 64 r4 rPC interpreted program counter, used for fetching instructions
76 #define rPC r4 define
83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
[all...] |
| /dalvik/vm/compiler/codegen/x86/ |
| H A D | LowerObject.cpp | 183 rPC += 2;
194 rPC += 2;
244 rPC += 1;
282 rPC += 1;
307 rPC += 1;
352 rPC += 2;
427 rPC += 2;
547 rPC += 3;
596 rPC += 3;
621 move_imm_to_mem(OpndSize_32, (int)(rPC
[all...] |
| /dalvik/vm/compiler/template/mips/ |
| H A D | TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S | 25 # a0 = this, a1 = returnCell, a2 = predictedChainCell, rPC = dalvikCallsite
56 * rPC <- dPC
|