Searched refs:CPU (Results 26 - 50 of 255) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp65 StringRef CPU,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Subtarget(TT, CPU, FS, is64bit),
84 StringRef CPU, StringRef FS,
88 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
94 StringRef CPU, StringRef FS,
98 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DNVPTXTargetMachine.h51 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU,
107 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU,
116 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU,
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp36 StringRef CPU, StringRef FS,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
56 StringRef CPU, StringRef FS,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
66 StringRef CPU, StringRef FS,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DPPCSubtarget.cpp29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, argument
31 : PPCGenSubtargetInfo(TT, CPU, FS)
48 std::string CPUName = CPU;
60 // Initialize scheduling itinerary for the specified CPU.
H A DPPCTargetMachine.h42 StringRef CPU, StringRef FS, const TargetOptions &Options,
79 StringRef CPU, StringRef FS, const TargetOptions &Options,
90 StringRef CPU, StringRef FS, const TargetOptions &Options,
/external/webkit/Source/JavaScriptCore/wtf/
H A DTCSpinLock.h37 #if (CPU(X86) || CPU(X86_64) || CPU(PPC)) && (COMPILER(GCC) || COMPILER(MSVC))
66 #if CPU(X86) || CPU(X86_64)
96 #if CPU(X86) || CPU(X86_64)
107 #if OS(DARWIN) || CPU(PPC)
147 #if CPU(X86) || CPU(X86_6
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H A DPlatform.h32 CPU. This macro will be phased out in favor of platform adaptation
41 /* CPU() - the target CPU architecture */
42 #define CPU(WTF_FEATURE) (defined WTF_CPU_##WTF_FEATURE && WTF_CPU_##WTF_FEATURE) macro
122 /* ==== CPU() - the target CPU architecture ==== */
124 /* This also defines CPU(BIG_ENDIAN) or CPU(MIDDLE_ENDIAN) or neither, as appropriate. */
126 /* CPU(ALPHA) - DEC Alpha */
131 /* CPU(IA6
[all...]
/external/chromium/base/
H A Dcpu.h16 class BASE_API CPU { class in namespace:base
19 CPU();
21 // Accessors for CPU information.
H A Dcpu_unittest.cc9 // Tests whether we can run extended instructions represented by the CPU
11 // MMX, SSE, etc.) supported by the CPU and sees we can run them without
14 TEST(CPU, RunExtendedInstructions) {
16 // Retrieve the CPU information.
17 base::CPU cpu;
H A Dcpu.cc17 CPU::CPU() function in class:base::CPU
82 void CPU::Initialize() {
88 // valid Ids in CPUInfo[0] and the CPU identification string in
89 // the other three array elements. The CPU identification string is
102 // Interpret CPU feature information.
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h35 std::string ParseARMTriple(StringRef TT, StringRef CPU);
40 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
/external/llvm/lib/Target/CellSPU/
H A DSPUSubtarget.cpp25 SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU, argument
27 SPUGenSubtargetInfo(TT, CPU, FS),
39 // Initialize scheduling itinerary for the specified CPU.
H A DSPUSubtarget.h56 SPUSubtarget(const std::string &TT, const std::string &CPU,
61 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DSPUTargetMachine.cpp35 StringRef CPU, StringRef FS,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 Subtarget(TT, CPU, FS),
34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeSubtarget.h45 MBlazeSubtarget(const std::string &TT, const std::string &CPU,
50 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DMBlazeTargetMachine.cpp36 StringRef CPU, StringRef FS, const TargetOptions &Options,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 Subtarget(TT, CPU, FS),
35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/webkit/Source/JavaScriptCore/heap/
H A DMachineStackMarker.cpp312 #if CPU(X86)
314 #elif CPU(X86_64)
316 #elif CPU(PPC)
318 #elif CPU(PPC64)
320 #elif CPU(ARM)
326 #elif OS(WINDOWS) && CPU(X86)
338 #if CPU(X86)
341 #elif CPU(X86_64)
344 #elif CPU(PPC)
347 #elif CPU(PPC6
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/external/llvm/lib/Target/Mips/
H A DMipsSubtarget.cpp27 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
30 MipsGenSubtargetInfo(TT, CPU, FS),
36 std::string CPUName = CPU;
43 // Initialize scheduling itinerary for the specified CPU.
H A DMipsTargetMachine.h44 StringRef CPU, StringRef FS, const TargetOptions &Options,
89 StringRef CPU, StringRef FS, const TargetOptions &Options,
100 StringRef CPU, StringRef FS, const TargetOptions &Options,
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp41 StringRef CPU, StringRef FS,
45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
46 Subtarget(TT, CPU, FS),
57 StringRef CPU, StringRef FS,
61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
76 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
83 StringRef CPU, StringRef FS,
87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/X86/
H A DX86TargetMachine.cpp34 StringRef CPU, StringRef FS,
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
57 StringRef CPU, StringRef FS,
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
73 StringRef CPU, StringRef FS,
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
72 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp37 static std::string ParseMipsTriple(StringRef TT, StringRef CPU) { argument
54 if (CPU.empty() || CPU == "mips32") {
56 } else if (CPU == "mips32r2") {
60 if (CPU.empty() || CPU == "mips64") {
62 } else if (CPU == "mips64r2") {
81 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, argument
83 std::string ArchFS = ParseMipsTriple(TT,CPU);
91 InitMipsMCSubtargetInfo(X, TT, CPU, ArchF
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/external/qemu/android/build/
H A Dcommon.sh59 ## Normalize OS and CPU
62 CPU=`uname -m`
63 case "$CPU" in
64 i?86) CPU=x86
66 amd64) CPU=x86_64
68 powerpc) CPU=ppc
72 log2 "CPU=$CPU"
74 # at this point, the supported values for CPU are:
86 OS=darwin-$CPU
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/external/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.h37 StringRef CPU, StringRef FS, const TargetOptions &Options,
67 StringRef CPU, StringRef FS,
79 StringRef CPU, StringRef FS,
/external/blktrace/
H A Dbarrier.h30 #error Define store_barrier() for your CPU

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