Searched refs:getReg (Results 51 - 75 of 250) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
H A DHexagonVarargsCallingConvention.h57 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
69 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
113 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
125 State.addLoc(CCValAssign::getReg(ValNo, ValVT.getSimpleVT(), Reg,
H A DHexagonAsmPrinter.h64 unsigned RegNo = MO.getReg();
86 O << getRegisterName(MO1.getReg())
96 O << getRegisterName(MO1.getReg())
/external/dexmaker/src/dx/java/com/android/dx/dex/code/form/
H A DForm3rc.java92 unsignedFitsInShort(regs.get(0).getReg()) &&
101 int firstReg = (regs.size() == 0) ? 0 : regs.get(0).getReg();
H A DForm5rc.java91 unsignedFitsInShort(regs.get(0).getReg()) &&
100 int firstReg = (regs.size() == 0) ? 0 : regs.get(0).getReg();
/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DInterferenceRegisterMapper.java110 return interferes(oldSpec.getReg(), newReg, oldSpec.getCategory());
149 int r = oldToNew(oldSpec.getReg());
H A DSsaInsn.java115 return result != null && result.getReg() == reg;
143 result.getReg(), result.getType(), local);
H A DEscapeAnalysis.java129 if (e.regSet.get(reg.getReg())) {
232 escSet = new EscapeSet(result.getReg(), regCount, EscapeState.NONE);
238 escSet = new EscapeSet(result.getReg(), regCount, EscapeState.NONE);
263 escSet = new EscapeSet(result.getReg(), regCount,
272 escSet = new EscapeSet(result.getReg(), regCount,
277 escSet = new EscapeSet(result.getReg(), regCount,
283 escSet = new EscapeSet(result.getReg(), regCount,
296 escSet.regSet.set(result.getReg());
302 escSet = new EscapeSet(result.getReg(), regCount,
305 escSet = new EscapeSet(result.getReg(), regCoun
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H A DSsaMethod.java422 definitionList[insn.getResult().getReg()] = insn;
425 definitionList[phi.getResult().getReg()] = phi;
430 definitionList[insn.getResult().getReg()] = insn;
474 useList[rl.get(i).getReg()].add(insn);
499 int reg = oldSource.getReg();
503 int reg = newSource.getReg();
531 int reg = sources.get(i).getReg();
552 if (!useList[oldSources.get(i).getReg()].remove(insn)) {
582 definitionList[resultReg.getReg()] = null;
615 int reg = oldResult.getReg();
[all...]
/external/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp94 unsigned SrcReg = I->getOperand(i).getReg();
102 return I->getOperand(0).getReg();
152 return NewDef->getOperand(0).getReg();
205 return InsertedPHI->getOperand(0).getReg();
273 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
301 return NewDef->getOperand(0).getReg();
312 return PHI->getOperand(0).getReg();
349 return PHI->getOperand(0).getReg();
H A DRegisterScavenging.cpp154 unsigned Reg = MO.getReg();
179 unsigned Reg = MO.getReg();
286 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
288 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
295 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
336 if (MO.isReg() && MO.getReg() != 0 &&
337 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
338 Candidates.reset(MO.getReg());
H A DMachineLICM.cpp433 unsigned Reg = MO.getReg();
540 unsigned Reg = MO.getReg();
567 if (!MO.isReg() || MO.isDef() || !MO.getReg())
569 unsigned Reg = MO.getReg();
597 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
598 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
773 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
817 unsigned Reg = MO.getReg();
849 unsigned Reg = MO.getReg();
[all...]
H A DTargetInstrInfoImpl.cpp78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
79 unsigned Reg1 = MI->getOperand(Idx1).getReg();
80 unsigned Reg2 = MI->getOperand(Idx2).getReg();
171 MO.setReg(Pred[j].getReg());
229 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
262 unsigned FoldReg = FoldOp.getReg();
263 unsigned LiveReg = LiveOp.getReg();
271 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
272 return RC->contains(LiveOp.getReg()) ? RC : 0;
342 storeRegToStackSlot(*MBB, Pos, MO.getReg(), M
[all...]
/external/llvm/lib/Target/PowerPC/InstPrinter/
H A DPPCInstPrinter.cpp57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
91 unsigned CCReg = MI->getOperand(OpNo+1).getReg();
195 unsigned CCReg = MI->getOperand(OpNo).getReg();
215 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
230 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
243 if (MI->getOperand(OpNo).getReg() == PPC::R0)
270 const char *RegName = getRegisterName(Op.getReg());
/external/llvm/lib/MC/MCDisassembler/
H A DEDOperand.cpp146 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
166 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
168 unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
173 unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
223 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
250 return Inst.Inst->getOperand(MCOpIndex).getReg();
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp172 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
173 return 0x80 >> getPPCRegisterNumbering(MO.getReg());
184 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
185 return getPPCRegisterNumbering(MO.getReg());
/external/llvm/lib/Target/PowerPC/
H A DPPCCodeEmitter.cpp143 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
144 return 0x80 >> getPPCRegisterNumbering(MO.getReg());
254 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
255 return getPPCRegisterNumbering(MO.getReg());
/external/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp86 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
123 MI->getOperand(opNum+1).getReg() == SP::G0)
147 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
149 assert(MO.getReg() != SP::O7 &&
151 operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
253 return MachineLocation(MI->getOperand(0).getReg(),
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp233 unsigned Reg = MO.getReg();
243 unsigned Reg = MO.getReg();
306 unsigned Reg = MO.getReg();
346 if (MI->getOperand(1).getReg() == ARM::SP) {
380 unsigned BaseReg = MI->getOperand(0).getReg();
388 if (MI->getOperand(i).getReg() == BaseReg) {
402 unsigned BaseReg = MI->getOperand(1).getReg();
416 unsigned BaseReg = MI->getOperand(1).getReg();
436 OffsetReg = MI->getOperand(2).getReg();
496 if (MI->getOperand(1).getReg() !
[all...]
H A DARMAsmPrinter.cpp218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
231 unsigned Reg = MLoc.getReg();
338 unsigned Reg = MO.getReg();
431 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
447 unsigned Reg = MI->getOperand(OpNum).getReg();
474 unsigned RegBegin = MO.getReg();
488 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
513 unsigned Reg = MO.getReg();
522 unsigned Reg = MI->getOperand(OpNum).getReg();
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H A DARMExpandPseudoInsts.cpp79 assert(MO.isReg() && MO.getReg());
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
463 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
520 DstReg = MI.getOperand(OpIdx++).getReg();
544 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
593 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
617 unsigned DstReg = MI.getOperand(0).getReg();
694 MI.getOperand(1).getReg())
695 .addReg(MI.getOperand(2).getReg(),
698 .addReg(MI.getOperand(4).getReg());
[all...]
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp320 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
333 unsigned Reg = getReg(Decoder, Mips::CPU64RegsRegClassID, RegNo);
344 unsigned Reg = getReg(Decoder, Mips::CPURegsRegClassID, RegNo);
356 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
368 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
389 Reg = getReg(Decoder, Mips::CPURegsRegClassID, Reg);
390 Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
411 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
412 Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
450 unsigned Reg = getReg(Decode
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp508 unsigned getReg() const { function in class:__anon9445::ARMOperand
1440 Inst.addOperand(MCOperand::CreateReg(getReg()));
1445 Inst.addOperand(MCOperand::CreateReg(getReg()));
2333 OS << "<ccout " << getReg() << ">";
2385 OS << "<register " << getReg() << ">";
2545 int SrcReg = PrevOp->getReg();
4144 ((ARMOperand*)Operands[4])->getReg() ==
4145 ((ARMOperand*)Operands[3])->getReg())
4822 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4830 static_cast<ARMOperand*>(Operands[1])->getReg()
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp236 return MI.getOperand(Op).getReg() == ARM::CPSR;
409 unsigned Reg = MO.getReg();
439 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
714 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
715 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
847 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
930 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
931 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
[all...]
/external/dexmaker/src/dx/java/com/android/dx/ssa/back/
H A DFirstFitLocalCombiningAllocator.java168 regs.append(reg.getReg());
188 int ssaReg = ssaSpec.getReg();
253 if (!ssaRegsMapped.get(ssaSpec.getReg())
288 if (ssaRegsMapped.get(spec.getReg())) {
316 && !ssaRegsMapped.get(ssaSpec.getReg())
459 int moveReg = moveRegSpec.getReg();
481 int checkReg = checkRegSpec.getReg();
578 if (ssaRegsMapped.get(spec.getReg())) continue;
692 int ssaReg = ssaSpec.getReg();
702 ssaSpec.getReg(), ropRe
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H A DLivenessAnalyzer.java240 interference.add(regV, rs.getReg());
271 interference.add(phis.get(i).getResult().getReg(),
272 phis.get(j).getResult().getReg());

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