Searched defs:opcode (Results 26 - 50 of 100) sorted by relevance

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/dalvik/dx/src/com/android/dx/dex/code/
H A DTargetInsn.java34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position, argument
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) { argument
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest();
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
H A DCstInsn.java47 * @param opcode the opcode; one of the constants from {@link Dops}
54 public CstInsn(Dop opcode, SourcePosition position, argument
56 super(opcode, position, registers);
69 public DalvInsn withOpcode(Dop opcode) { argument
71 new CstInsn(opcode, getPosition(), getRegisters(), constant);
/dalvik/dx/src/com/android/dx/io/instructions/
H A DFillArrayDataPayloadDecodedInstruction.java39 int opcode, Object data, int size, int elementWidth) {
40 super(format, opcode, 0, null, 0, 0L);
51 int opcode, byte[] data) {
52 this(format, opcode, data, data.length, 1);
59 int opcode, short[] data) {
60 this(format, opcode, data, data.length, 2);
67 int opcode, int[] data) {
68 this(format, opcode, data, data.length, 4);
75 int opcode, long[] data) {
76 this(format, opcode, dat
38 FillArrayDataPayloadDecodedInstruction(InstructionCodec format, int opcode, Object data, int size, int elementWidth) argument
50 FillArrayDataPayloadDecodedInstruction(InstructionCodec format, int opcode, byte[] data) argument
58 FillArrayDataPayloadDecodedInstruction(InstructionCodec format, int opcode, short[] data) argument
66 FillArrayDataPayloadDecodedInstruction(InstructionCodec format, int opcode, int[] data) argument
74 FillArrayDataPayloadDecodedInstruction(InstructionCodec format, int opcode, long[] data) argument
[all...]
H A DOneRegisterDecodedInstruction.java31 public OneRegisterDecodedInstruction(InstructionCodec format, int opcode, argument
34 super(format, opcode, index, indexType, target, literal);
H A DRegisterRangeDecodedInstruction.java35 public RegisterRangeDecodedInstruction(InstructionCodec format, int opcode, argument
38 super(format, opcode, index, indexType, target, literal);
H A DTwoRegisterDecodedInstruction.java34 public TwoRegisterDecodedInstruction(InstructionCodec format, int opcode, argument
37 super(format, opcode, index, indexType, target, literal);
H A DFiveRegisterDecodedInstruction.java43 public FiveRegisterDecodedInstruction(InstructionCodec format, int opcode, argument
46 super(format, opcode, index, indexType, target, literal);
H A DFourRegisterDecodedInstruction.java40 public FourRegisterDecodedInstruction(InstructionCodec format, int opcode, argument
43 super(format, opcode, index, indexType, target, literal);
H A DThreeRegisterDecodedInstruction.java37 public ThreeRegisterDecodedInstruction(InstructionCodec format, int opcode, argument
40 super(format, opcode, index, indexType, target, literal);
/dalvik/dx/src/com/android/dx/rop/code/
H A DDexTranslationAdvice.java57 public boolean hasConstantOperation(Rop opcode, argument
67 opcode.getOpcode() == RegOps.SUB) {
77 switch (opcode.getOpcode()) {
102 public boolean requiresSourcesInOrder(Rop opcode, argument
105 return !disableSourcesInOrder && opcode.isCallLike()
H A DPlainCstInsn.java33 * @param opcode {@code non-null;} the opcode
39 public PlainCstInsn(Rop opcode, SourcePosition position, argument
42 super(opcode, position, result, sources, cst);
44 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
H A DPlainInsn.java35 * @param opcode {@code non-null;} the opcode
40 public PlainInsn(Rop opcode, SourcePosition position, argument
42 super(opcode, position, result, sources);
44 switch (opcode.getBranchingness()) {
51 if (result != null && opcode.getBranchingness() != Rop.BRANCH_NONE) {
61 * @param opcode {@code non-null;} the opcode
66 public PlainInsn(Rop opcode, SourcePosition position, RegisterSpec result, argument
68 this(opcode, positio
[all...]
H A DFillArrayDataInsn.java45 * @param opcode {@code non-null;} the opcode
51 public FillArrayDataInsn(Rop opcode, SourcePosition position, argument
55 super(opcode, position, null, sources);
57 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
H A DSwitchInsn.java35 * @param opcode {@code non-null;} the opcode
41 public SwitchInsn(Rop opcode, SourcePosition position, RegisterSpec result, argument
43 super(opcode, position, result, sources);
45 if (opcode.getBranchingness() != Rop.BRANCH_SWITCH) {
H A DThrowingCstInsn.java36 * @param opcode {@code non-null;} the opcode
42 public ThrowingCstInsn(Rop opcode, SourcePosition position, argument
45 super(opcode, position, null, sources, cst);
47 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
H A DThrowingInsn.java57 * @param opcode {@code non-null;} the opcode
62 public ThrowingInsn(Rop opcode, SourcePosition position, argument
65 super(opcode, position, null, sources);
67 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
/dalvik/vm/compiler/codegen/arm/FP/
H A DThumbVFP.cpp68 TemplateOpcode opcode; local
74 switch (mir->dalvikInsn.opcode) {
77 opcode = TEMPLATE_ADD_FLOAT_VFP;
81 opcode = TEMPLATE_SUB_FLOAT_VFP;
85 opcode = TEMPLATE_DIV_FLOAT_VFP;
89 opcode = TEMPLATE_MUL_FLOAT_VFP;
102 genDispatchToHandler(cUnit, opcode);
114 TemplateOpcode opcode; local
116 switch (mir->dalvikInsn.opcode) {
119 opcode
156 Opcode opcode = mir->dalvikInsn.opcode; local
[all...]
/dalvik/dexgen/src/com/android/dexgen/dex/code/
H A DCstInsn.java47 * @param opcode the opcode; one of the constants from {@link Dops}
54 public CstInsn(Dop opcode, SourcePosition position, argument
56 super(opcode, position, registers);
69 public DalvInsn withOpcode(Dop opcode) { argument
71 new CstInsn(opcode, getPosition(), getRegisters(), constant);
/dalvik/dexgen/src/com/android/dexgen/rop/code/
H A DFillArrayDataInsn.java45 * @param opcode {@code non-null;} the opcode
51 public FillArrayDataInsn(Rop opcode, SourcePosition position, argument
55 super(opcode, position, null, sources);
57 if (opcode.getBranchingness() != Rop.BRANCH_NONE) {
H A DSwitchInsn.java35 * @param opcode {@code non-null;} the opcode
41 public SwitchInsn(Rop opcode, SourcePosition position, RegisterSpec result, argument
43 super(opcode, position, result, sources);
45 if (opcode.getBranchingness() != Rop.BRANCH_SWITCH) {
H A DThrowingCstInsn.java35 * @param opcode {@code non-null;} the opcode
41 public ThrowingCstInsn(Rop opcode, SourcePosition position, argument
44 super(opcode, position, null, sources, cst);
46 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
H A DThrowingInsn.java57 * @param opcode {@code non-null;} the opcode
62 public ThrowingInsn(Rop opcode, SourcePosition position, argument
65 super(opcode, position, null, sources);
67 if (opcode.getBranchingness() != Rop.BRANCH_THROW) {
/dalvik/libdex/
H A DInstrUtils.cpp21 * automatically by the opcode-gen tool. Any edits to the generated
29 * Table that maps each opcode to the full width of instructions that
30 * use that opcode, in (16-bit) code units. Unimplemented opcodes as
31 * well as the "breakpoint" opcode have a width of zero.
34 // BEGIN(libdex-widths); GENERATED AUTOMATICALLY BY opcode-gen
55 * Table that maps each opcode to the flags associated with that
56 * opcode.
59 // BEGIN(libdex-flags); GENERATED AUTOMATICALLY BY opcode-gen
320 * Table that maps each opcode to the instruction format associated
321 * that opcode
493 Opcode opcode = dexOpcodeFromCodeUnit(inst); local
[all...]
/dalvik/vm/compiler/codegen/arm/
H A DArchFactory.cpp106 static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpcode opcode) argument
118 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
119 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
121 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
122 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
H A DArchUtility.cpp28 static char * decodeRegList(ArmOpcode opcode, int vector, char *buf) argument
36 if (opcode == kThumbPush && i == 8) {
38 } else if (opcode == kThumbPop && i == 8) {
219 decodeRegList(lir->opcode, operand, tbuf);
305 switch(lir->opcode) {
375 buildInsnString(EncodingMap[lir->opcode].name, lir, opName,
377 buildInsnString(EncodingMap[lir->opcode].fmt, lir, buf, baseAddr,
433 * de is an invalid opcode for arm.

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