/dalvik/vm/compiler/codegen/x86/ |
H A D | LowerReturn.cpp | 50 move_reg_to_reg(OpndSize_32, PhysicalReg_FP, true, 10, false); 51 move_mem_to_reg(OpndSize_32, -sizeofStackSaveArea+offStackSaveArea_prevFrame, PhysicalReg_FP, true, PhysicalReg_FP, true); //update rFP 53 move_mem_to_reg(OpndSize_32, -sizeofStackSaveArea+offStackSaveArea_method, PhysicalReg_FP, true, 6, false); 54 compare_imm_reg(OpndSize_32, 0, 6, false); 58 move_reg_to_mem(OpndSize_32, 6, false, offsetof(Thread, interpSave.method), 2, false); 60 move_mem_to_reg(OpndSize_32, offMethod_clazz, 6, false, 14, false); 62 move_reg_to_mem(OpndSize_32, PhysicalReg_FP, true, offThread_curFrame, 3, false); 64 move_mem_to_reg(OpndSize_32, offClassObject_pDvmDex, 14, false, 7, false); 65 move_reg_to_mem(OpndSize_32, 7, false, offsetof(Thread, interpSave.methodClassDex), 2, false); 67 compare_imm_mem(OpndSize_32, [all...] |
H A D | LowerInvoke.cpp | 94 get_virtual_reg(vD, OpndSize_32, 5, false); 97 move_mem_to_reg(OpndSize_32, offObject_clazz, 5, false, 6, false); //clazz of "this" 98 move_mem_to_reg(OpndSize_32, offClassObject_vtable, 6, false, 7, false); //vtable 102 move_mem_to_reg(OpndSize_32, methodIndex*4, 7, false, PhysicalReg_ECX, true); 152 move_imm_to_reg(OpndSize_32, (int) calleeMethod, PhysicalReg_ECX, true); 173 move_mem_to_reg(OpndSize_32, offMethod_name, PhysicalReg_EAX, true, PhysicalReg_EDX, true); //method name 197 get_virtual_reg(vD, OpndSize_32, 5, false); 202 move_imm_to_reg(OpndSize_32, (int) calleeMethod, PhysicalReg_ECX, true); 239 move_imm_to_reg(OpndSize_32, (int) calleeMethod, PhysicalReg_ECX, true); 283 get_virtual_reg(vD, OpndSize_32, [all...] |
H A D | LowerMove.cpp | 34 get_virtual_reg(vB, OpndSize_32, 1, false/*isPhysical*/); 35 set_virtual_reg(vA, OpndSize_32, 1, false); 46 get_virtual_reg(vB, OpndSize_32, 1, false); 47 set_virtual_reg(vA, OpndSize_32, 1, false); 58 get_virtual_reg(vB, OpndSize_32, 1, false); 59 set_virtual_reg(vA, OpndSize_32, 1, false); 108 get_return_value(OpndSize_32, 1, false); 109 set_virtual_reg(vA, OpndSize_32, 1, false); 141 move_mem_to_reg(OpndSize_32, offThread_exception, 2, false, 3, false); 142 move_imm_to_mem(OpndSize_32, [all...] |
H A D | LowerObject.cpp | 36 get_virtual_reg(vA, OpndSize_32, 1, false); //object 52 compare_imm_reg(OpndSize_32, 0, 1, false); 67 move_mem_to_reg(OpndSize_32, tmp*4, 4, false, PhysicalReg_EAX, true); 68 compare_imm_reg(OpndSize_32, 0, PhysicalReg_EAX, true); 75 move_imm_to_reg(OpndSize_32, tmp, PhysicalReg_EAX, true); 82 move_imm_to_reg(OpndSize_32, (int)classPtr, PhysicalReg_EAX, true); 90 move_mem_to_reg(OpndSize_32, offObject_clazz, 1, false, 6, false); //object->clazz 106 move_reg_to_mem(OpndSize_32, 6, false, 0, PhysicalReg_ESP, true); 107 move_reg_to_mem(OpndSize_32, PhysicalReg_EAX, true, 4, PhysicalReg_ESP, true); //resolved class 115 move_reg_to_reg(OpndSize_32, PhysicalReg_EA [all...] |
H A D | LowerAlu.cpp | 35 get_virtual_reg(vB, OpndSize_32, 1, false); 36 alu_unary_reg(OpndSize_32, neg_opc, 1, false); 37 set_virtual_reg(vA, OpndSize_32, 1, false); 47 get_virtual_reg(vB, OpndSize_32, 1, false); 48 alu_unary_reg(OpndSize_32, not_opc, 1, false); 49 set_virtual_reg(vA, OpndSize_32, 1, false); 87 get_virtual_reg(vB, OpndSize_32, 1, false); 88 alu_binary_imm_reg(OpndSize_32, add_opc, 0x80000000, 1, false); 89 set_virtual_reg(vA, OpndSize_32, 1, false); 115 get_virtual_reg(vB, OpndSize_32, PhysicalReg_EA [all...] |
H A D | LowerConst.cpp | 52 set_VR_to_imm(vA, OpndSize_32, (int) strPtr ); 70 set_VR_to_imm(vA, OpndSize_32, tmp); 80 set_VR_to_imm(vA, OpndSize_32, (s2)BBBB); 91 set_VR_to_imm(vA, OpndSize_32, (s4)tmp); 101 set_VR_to_imm(vA, OpndSize_32, (s4)tmp<<16); //?? 111 set_VR_to_imm(vA, OpndSize_32, (s2)tmp); 112 set_VR_to_imm(vA+1, OpndSize_32, (s2)tmp>>31); 123 set_VR_to_imm(vA, OpndSize_32, (s4)tmp); 124 set_VR_to_imm(vA+1, OpndSize_32, (s4)tmp>>31); 135 set_VR_to_imm(vA, OpndSize_32, (s [all...] |
H A D | LowerJump.cpp | 264 item->size = OpndSize_32; 284 item->size = OpndSize_32; 305 item->size = OpndSize_32; 326 item->size = OpndSize_32; 422 return OpndSize_32; 440 assert(size == OpndSize_32); 483 *immSize = OpndSize_32; 497 *immSize = OpndSize_32; 502 *immSize = OpndSize_32; 510 *immSize = OpndSize_32; [all...] |
H A D | LowerGetPut.cpp | 44 get_virtual_reg(vref, OpndSize_32, 1, false); //array 45 get_virtual_reg(vindex, OpndSize_32, 2, false); //index 67 move_mem_disp_scale_to_reg(OpndSize_32, 1, false, offArrayObject_contents, 2, false, 4, 4, false); 88 set_virtual_reg(vA, OpndSize_32, 4, false); 195 get_virtual_reg(vref, OpndSize_32, 1, false); //array 196 get_virtual_reg(vindex, OpndSize_32, 2, false); //index 221 get_virtual_reg(vA, OpndSize_32, 4, false); 224 move_reg_to_mem_disp_scale(OpndSize_32, 4, false, 1, false, offArrayObject_contents, 2, false, 4); 339 get_virtual_reg(vref, OpndSize_32, 1, false); //array 343 compare_imm_reg(OpndSize_32, [all...] |
H A D | NcgAot.cpp | 35 move_imm_to_mem(OpndSize_32, (int)rPC, 44 move_imm_to_reg(OpndSize_32, (int)funcPtr, C_SCRATCH_1, isScratchPhysical); 55 move_imm_to_reg(OpndSize_32, (int)funcPtr, C_SCRATCH_1, isScratchPhysical); 73 move_imm_to_reg(OpndSize_32, (int)funcPtr, C_SCRATCH_1, isScratchPhysical); 90 move_imm_to_reg(OpndSize_32, (int)funcPtr, C_SCRATCH_1, isScratchPhysical); 102 move_imm_to_reg(OpndSize_32, (int)funcPtr, C_SCRATCH_1, isScratchPhysical);
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H A D | LowerHelper.cpp | 28 OpndSize can be OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64 538 op->lop.opnd1.size = OpndSize_32; 798 dump_mem_reg(m, ATOM_NORMAL, OpndSize_32, disp, base_reg, isBasePhysical, 808 dump_mem_scale_reg(m, OpndSize_32, 831 assert(srcSize == OpndSize_32 && dstSize == OpndSize_64); 833 dump_reg_reg(m, ATOM_NORMAL, OpndSize_32, PhysicalReg_EAX, true, PhysicalReg_EDX, true, LowOpndRegType_gp); 895 size = OpndSize_32; 907 dumpImmToMem(vA, OpndSize_32, tmpValue[0]); 908 //dumpImmToMem(vA+1, OpndSize_32, 0); //CHECK necessary? will overwrite vA+1!!! 923 dumpImmToMem(vA, OpndSize_32, tmpValu [all...] |
H A D | CodegenInterface.cpp | 614 unconditional_jump_int(0, OpndSize_32); 642 move_imm_to_reg(OpndSize_32, (int) (cUnit->method->insns + offset), P_GPR_1, true); 645 //move_imm_to_reg(OpndSize_32, (int) (cUnit->method->insns + offset), P_GPR_1, true); /* used when unchaining */ 664 move_imm_to_reg(OpndSize_32, (int) (cUnit->method->insns + offset), P_GPR_1, true); 667 //move_imm_to_reg(OpndSize_32, (int) (cUnit->method->insns + offset), P_GPR_1, true); /* used when unchaining */ 683 move_imm_to_reg(OpndSize_32, (int) (cUnit->method->insns + offset), P_GPR_1, true); 686 //move_imm_to_reg(OpndSize_32, (int) (cUnit->method->insns + offset), P_GPR_1, true); /* used when unchaining */ 702 move_imm_to_reg(OpndSize_32, (int) (callee->insns), P_GPR_1, true); 705 //move_imm_to_reg(OpndSize_32, (int) (callee->insns), P_GPR_1, true); /* used when unchaining */ 785 get_virtual_reg(mir->dalvikInsn.vA, OpndSize_32, P_GPR_ [all...] |
H A D | AnalysisO1.cpp | 95 return OpndSize_32; 120 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regA == regB) return OVERLAP_B_COVER_LOW_OF_A; 121 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regB == regA + 1) return OVERLAP_B_COVER_HIGH_OF_A; 122 if(getRegSize(tA) == OpndSize_32 && getRegSize(tB) == OpndSize_64 && (regA == regB || regA == regB+1)) return OVERLAP_B_COVER_A; 132 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regA == regB) 134 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regB == regA+1) 140 if(getRegSize(tA) == OpndSize_32 && getRegSize(tB) == OpndSize_64 && regA == regB) 142 if(getRegSize(tA) == OpndSize_32 && getRegSize(tB) == OpndSize_64 && regA == regB+1) 150 if(getRegSize(tB) == OpndSize_32) return true; 603 move_imm_to_mem(OpndSize_32, cUni [all...] |
H A D | BytecodeVisitor.cpp | 523 setVRToNonConst(constWorklist[k], OpndSize_32); 563 setVRToConst(vA, OpndSize_32, tmpValue); 751 setVRToConst(vA, OpndSize_32, tmpValue); 827 setVRToConst(vA, OpndSize_32, tmpValue); 869 setVRToConst(vA, OpndSize_32, tmpValue); 921 setVRToConst(vA, OpndSize_32, tmpValue); 973 setVRToConst(vA, OpndSize_32, tmpValue); 1034 setVRToConst(vA, OpndSize_32, tmpValue); 1047 setVRToConst(vA, OpndSize_32, tmpValue); 1061 setVRToConst(vA, OpndSize_32, tmpValu [all...] |
H A D | Lower.cpp | 356 move_mem_to_reg(OpndSize_32, 0, PhysicalReg_ESP, true, PhysicalReg_EDX, true);
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/dalvik/vm/compiler/codegen/x86/libenc/ |
H A D | enc_prvt.h | 141 #define EAX {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_EAX} 147 #define ECX {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_ECX} 153 #define EDX {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_EDX} 158 #define ESI {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_ESI} 163 #define EDI {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_EDI} 170 #define r32 {OpndKind_GPReg, OpndSize_32, OpndExt_Any, RegName_Null} 177 #define r_m32 {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, OpndExt_Any, RegName_Null} 181 #define r_m32s {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, OpndExt_Signed, RegName_Null} 185 #define r_m32u {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_32, OpndExt_Zero, RegName_Null} 192 #define m32 {OpndKind_Mem, OpndSize_32, OpndExt_An [all...] |
H A D | enc_defs.h | 187 RegName_EAX=REGNAME(OpndKind_GPReg,OpndSize_32,0), 188 RegName_ECX=REGNAME(OpndKind_GPReg,OpndSize_32,1), 189 RegName_EDX=REGNAME(OpndKind_GPReg,OpndSize_32,2), 190 RegName_EBX=REGNAME(OpndKind_GPReg,OpndSize_32,3), 191 RegName_ESP=REGNAME(OpndKind_GPReg,OpndSize_32,4), 192 RegName_EBP=REGNAME(OpndKind_GPReg,OpndSize_32,5), 193 RegName_ESI=REGNAME(OpndKind_GPReg,OpndSize_32,6), 194 RegName_EDI=REGNAME(OpndKind_GPReg,OpndSize_32,7), 197 RegName_R8D = REGNAME(OpndKind_GPReg,OpndSize_32,8), 198 RegName_R9D = REGNAME(OpndKind_GPReg,OpndSize_32, [all...] |
H A D | dec_base.cpp | 262 opnd_size = OpndSize_32; 266 opnd_size = OpndSize_32; // so there is no compiler warning 492 index = getRegName(OpndKind_GPReg, OpndSize_32, EXTEND_REG(sib.index, x)); //Android x86: OpndDesc.size 499 base = getRegName(OpndKind_GPReg, OpndSize_32, EXTEND_REG(sib.base, b)); //Android x86: OpndDesc.size 506 base = getRegName(OpndKind_GPReg, OpndSize_32, EXTEND_REG(modrm.rm, b)); //Android x86: OpndDesc.size
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H A D | enc_wrapper.cpp | 89 if(opnd.size() != OpndSize_32) { 303 add_r(args, reg, OpndSize_32); 451 add_r(args, reg, OpndSize_32); 465 add_r(args, reg, OpndSize_32); 479 add_r(args, reg2, OpndSize_32); //destination 493 add_r(args, reg2, OpndSize_32); //destination 509 if(opnd.size() != OpndSize_32) {
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H A D | encoder.cpp | 120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any
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H A D | enc_base.h | 347 * @brief Creates immediate operand of OpndSize_32. 350 m_kind(OpndKind_Imm), m_size(OpndSize_32), m_ext(ext), m_imm64(ival)
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H A D | enc_defs_ext.h | 43 OpndSize_32 = 0x04, enumerator in enum:OpndSize
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H A D | enc_base.cpp | 53 1, // OpndSize_32 = 0x4, 882 { "Sz32", OpndSize_32 },
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H A D | enc_tabl.cpp | 1884 else if (sz==OpndSize_32) {imm_encode = id; coff_encode=cd; }
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