Searched refs:OpndSize_8 (Results 1 - 14 of 14) sorted by relevance

/dalvik/vm/compiler/codegen/x86/libenc/
H A Denc_prvt.h138 #define AL {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_AL}
139 #define AH {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_AH}
146 #define CL {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_CL}
168 #define r8 {OpndKind_GPReg, OpndSize_8, OpndExt_Any, RegName_Null}
175 #define r_m8 {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, OpndExt_Any, RegName_Null}
179 #define r_m8s {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, OpndExt_Signed, RegName_Null}
183 #define r_m8u {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_8, OpndExt_Zero, RegName_Null}
190 #define m8 {OpndKind_Mem, OpndSize_8, OpndExt_Any, RegName_Null}
198 #define imm8 {OpndKind_Imm, OpndSize_8, OpndExt_Any, RegName_Null}
202 #define imm8s {OpndKind_Imm, OpndSize_8, OpndExt_Signe
[all...]
H A Denc_defs.h227 RegName_AL=REGNAME(OpndKind_GPReg,OpndSize_8,0),
228 RegName_CL=REGNAME(OpndKind_GPReg,OpndSize_8,1),
229 RegName_DL=REGNAME(OpndKind_GPReg,OpndSize_8,2),
230 RegName_BL=REGNAME(OpndKind_GPReg,OpndSize_8,3),
234 RegName_AH=REGNAME(OpndKind_GPReg,OpndSize_8,4),
236 RegName_CH=REGNAME(OpndKind_GPReg,OpndSize_8,5),
237 RegName_DH=REGNAME(OpndKind_GPReg,OpndSize_8,6),
238 RegName_BH=REGNAME(OpndKind_GPReg,OpndSize_8,7),
240 RegName_SPL=REGNAME(OpndKind_GPReg,OpndSize_8,4),
241 RegName_BPL=REGNAME(OpndKind_GPReg,OpndSize_8,
[all...]
H A Dencoder.cpp120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any
H A Denc_base.h364 * @brief Creates immediate operand of OpndSize_8.
367 m_kind(OpndKind_Imm), m_size(OpndSize_8), m_ext(ext), m_imm64(ival)
H A Denc_defs_ext.h41 OpndSize_8 = 0x01, enumerator in enum:OpndSize
H A Denc_wrapper.cpp231 add_r(args, reg, OpndSize_8);
351 add_imm(args, OpndSize_8, imm, true/*is_signed*/);
382 size = OpndSize_8;
H A Ddec_base.cpp252 opnd_size = OpndSize_8;
H A Denc_base.cpp50 3, // OpndSize_8 = 0x1,
880 { "Sz8", OpndSize_8 },
H A Denc_tabl.cpp1882 if (sz==OpndSize_8) {imm_encode = ib; coff_encode=cb; }
/dalvik/vm/compiler/codegen/x86/
H A DLowerGetPut.cpp79 movez_mem_disp_scale_to_reg(OpndSize_8, 1, false, offArrayObject_contents, 2, false, 1, 4, false);
82 moves_mem_disp_scale_to_reg(OpndSize_8, 1, false, offArrayObject_contents, 2, false, 1, 4, false);
230 move_reg_to_mem_disp_scale(OpndSize_8, 4, false, 1, false, offArrayObject_contents, 2, false, 1);
424 move_reg_to_mem_disp_scale(OpndSize_8, scratchReg, isPhysical, scratchReg, isPhysical, 0, tgtAddrReg, targetPhysical, 1);
432 move_reg_to_mem_disp_scale(OpndSize_8, scratchReg, isPhysical, scratchReg, isPhysical, 0, tgtAddrReg, isPhysical, 1);
439 move_reg_to_mem_disp_scale(OpndSize_8, scratchReg, isScratchPhysical, scratchReg, isScratchPhysical, 0, tgtAddrReg, isTgtPhysical, 1);
H A DLowerJump.cpp85 if(immSize == OpndSize_8) { //-128 to 127
418 if(target-MIN_JCC_SIZE < 128 && target-MAX_JCC_SIZE >= -128) return OpndSize_8;
430 if(size == OpndSize_8) return 2;
435 if(size == OpndSize_8) return 2;
444 assert(size != OpndSize_8);
470 since the lable is only used within a single bytecode, we assume OpndSize_8 is big enough
486 *immSize = OpndSize_8;
H A DLowerObject.cpp463 movez_mem_to_reg(OpndSize_8, 1, 5, false, 6, false);
H A DCodegenInterface.cpp882 callsiteInfo->misPredBranchOver = (LIR*)conditional_jump_int(Condition_NE, 0, OpndSize_8);
H A DLowerInvoke.cpp71 updateJumpInst(streamMisPred, OpndSize_8, relativeNCG);

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