Searched refs:CPU (Results 1 - 25 of 255) sorted by relevance

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/external/v8/src/ia32/
H A Dcpu-ia32.cc28 // CPU specific code for ia32 independent of OS goes here.
44 void CPU::SetUp() {
49 bool CPU::SupportsCrankshaft() {
54 void CPU::FlushICache(void* start, size_t size) {
58 // is patched on an intel CPU the core performing the patching will have its
76 void CPU::DebugBreak() {
/external/v8/src/x64/
H A Dcpu-x64.cc28 // CPU specific code for x64 independent of OS goes here.
44 void CPU::SetUp() {
49 bool CPU::SupportsCrankshaft() {
54 void CPU::FlushICache(void* start, size_t size) {
58 // is patched on an intel CPU the core performing the patching will have its
76 void CPU::DebugBreak() {
/external/llvm/lib/Target/XCore/
H A DXCoreSubtarget.cpp27 const std::string &CPU, const std::string &FS)
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
26 XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
H A DXCoreSubtarget.h34 XCoreSubtarget(const std::string &TT, const std::string &CPU,
39 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DXCoreTargetMachine.cpp24 StringRef CPU, StringRef FS,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Sparc/
H A DSparcSubtarget.cpp26 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, argument
28 SparcGenSubtargetInfo(TT, CPU, FS),
35 std::string CPUName = CPU;
H A DSparcTargetMachine.cpp29 StringRef CPU, StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
79 StringRef TT, StringRef CPU,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
91 StringRef TT, StringRef CPU,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DSparcSubtarget.h34 SparcSubtarget(const std::string &TT, const std::string &CPU,
43 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/external/llvm/lib/Target/MSP430/
H A DMSP430Subtarget.cpp27 const std::string &CPU,
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
26 MSP430Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
H A DMSP430Subtarget.h33 MSP430Subtarget(const std::string &TT, const std::string &CPU,
38 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DMSP430TargetMachine.cpp29 StringRef CPU,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp23 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument
42 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
47 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
49 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { argument
51 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
74 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
86 KV.Key = CPU.data();
89 if (Found == ProcSchedModel+NumProcs || StringRef(Found->Key) != CPU) {
90 errs() << "'" << CPU
100 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) cons
[all...]
/external/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h39 uint64_t FeatureBits; // Feature bits for current CPU + FS
42 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
61 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
63 uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
73 /// getSchedModelForCPU - Get the machine model of a CPU.
75 const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
77 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
79 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp35 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, argument
37 :NVPTXGenSubtargetInfo(TT, "", FS), // Don't pass CPU to subtarget,
44 // Provide the default CPU if none
48 if (FS.empty() && CPU.empty())
50 else if (!CPU.empty())
51 TargetName = CPU;
/external/v8/src/arm/
H A Dcpu-arm.cc28 // CPU specific code for arm independent of OS goes here.
44 void CPU::SetUp() {
49 bool CPU::SupportsCrankshaft() {
54 void CPU::FlushICache(void* start, size_t size) {
110 void CPU::DebugBreak() {
/external/v8/src/
H A Dcpu.h45 // CPU
53 class CPU : public AllStatic { class in namespace:v8::internal
/external/v8/src/mips/
H A Dcpu-mips.cc28 // CPU specific code for arm independent of OS goes here.
50 void CPU::SetUp() {
55 bool CPU::SupportsCrankshaft() {
60 void CPU::FlushICache(void* start, size_t size) {
91 void CPU::DebugBreak() {
/external/qemu/distrib/
H A Dupdate-audio.sh27 CPU=`uname -p`
28 if [ "$CPU" == "i386" ] ; then
35 CPU=`uname -m`
36 case "$CPU" in
38 CPU=x86
41 OS=linux-$CPU
/external/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp41 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument
42 HexagonGenSubtargetInfo(TT, CPU, FS),
43 CPUString(CPU.str()) {
64 // Initialize scheduling itinerary for the specified CPU.
/external/llvm/lib/Target/MBlaze/
H A DMBlazeSubtarget.cpp27 const std::string &CPU,
29 MBlazeGenSubtargetInfo(TT, CPU, FS),
34 std::string CPUName = CPU;
39 // Only use instruction scheduling if the selected CPU has an instruction
40 // itinerary (the default CPU is the only one that doesn't).
42 DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n");
44 // Initialize scheduling itinerary for the specified CPU.
26 MBlazeSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
/external/llvm/lib/Target/CppBackend/
H A DCPPTargetMachine.h26 StringRef CPU, StringRef FS, const TargetOptions &Options,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/clang/include/clang/Basic/
H A DTargetOptions.h30 /// If given, the name of the target CPU to generate code for.
31 std::string CPU; member in class:clang::TargetOptions
/external/webkit/Source/JavaScriptCore/assembler/
H A DARMv7Assembler.cpp28 #if ENABLE(ASSEMBLER) && CPU(ARM_THUMB2)
/external/webkit/Source/WebCore/page/
H A DNavigatorBase.cpp38 #if OS(MAC_OS_X) && (CPU(PPC) || CPU(PPC64))
40 #elif OS(MAC_OS_X) && (CPU(X86) || CPU(X86_64))
/external/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp40 StringRef CPU, StringRef FS, const TargetOptions &Options,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, isLittle, RM),
63 StringRef CPU, StringRef FS, const TargetOptions &Options,
66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
72 StringRef CPU, StringRef FS, const TargetOptions &Options,
75 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
39 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
62 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
71 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument

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