Searched refs:CP0TCSt_TCU3 (Results 1 - 2 of 2) sorted by relevance

/external/qemu/target-mips/
H A Dcpu.h148 #define CP0TCSt_TCU3 31 macro
H A Dtranslate_init.c280 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |

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