| /external/javassist/src/main/javassist/bytecode/ |
| H A D | Opcode.java | 95 int FDIV = 110; field in interface:Opcode
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
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| /external/valgrind/main/none/tests/ppc32/ |
| H A D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator in enum:__anon14761
985 case FDIV:
1111 case FDIV:
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| /external/valgrind/main/none/tests/ppc64/ |
| H A D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator in enum:__anon14788
985 case FDIV:
1111 case FDIV:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 485 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
|
| H A D | SelectionDAGDumper.cpp | 179 case ISD::FDIV: return "fdiv";
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| H A D | LegalizeVectorOps.cpp | 182 case ISD::FDIV:
|
| H A D | LegalizeFloatTypes.cpp | 71 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
854 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
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| H A D | LegalizeVectorTypes.cpp | 100 case ISD::FDIV:
541 case ISD::FDIV:
1308 case ISD::FDIV:
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| H A D | FastISel.cpp | 962 return SelectBinaryOp(I, ISD::FDIV);
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| H A D | SelectionDAG.cpp | 2802 case ISD::FDIV:
3071 case ISD::FDIV:
3109 case ISD::FDIV:
3149 case ISD::FDIV:
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| H A D | LegalizeDAG.cpp | 3038 case ISD::FDIV:
3675 case ISD::FDIV:
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| H A D | DAGCombiner.cpp | 431 case ISD::FDIV:
499 case ISD::FDIV:
1134 case ISD::FDIV: return visitFDIV(N);
6083 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6112 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
8454 N->getOpcode() == ISD::FDIV) {
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| H A D | TargetLowering.cpp | 637 case ISD::FDIV:
|
| /external/javassist/src/main/javassist/bytecode/analysis/ |
| H A D | Executor.java | 348 case FDIV:
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| H A D | MBlazeDisassembler.cpp | 232 case 0x180: return MBlaze::FDIV;
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1095 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1098 setOperationAction(ISD::FDIV, MVT::f64, Expand);
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| /external/javassist/src/main/javassist/compiler/ |
| H A D | CodeGen.java | 937 '/', DDIV, FDIV, LDIV, IDIV,
|
| /external/dexmaker/lib/ |
| H A D | jarjar.jar | META-INF/ META-INF/MANIFEST.MF com/ com/tonicsystems/ com/tonicsystems/jarjar/ com/tonicsystems/jarjar/AbstractDepHandler ... |
| /external/llvm/lib/Target/CellSPU/ |
| H A D | SPUISelLowering.cpp | 346 // FDIV on SPU requires custom lowering
347 setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
459 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
| H A D | org.objectweb.asm_3.2.0.v200909071300.jar | META-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ... |
| H A D | org.eclipse.equinox.p2.repository.tools_2.0.1.R36x_v20100823.jar | META-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ... |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 145 setOperationAction(ISD::FDIV, VT, Expand);
476 // FIXME: Code duplication: FDIV and FREM are expanded always, see
478 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
557 setTargetDAGCombine(ISD::FDIV);
8983 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 725 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
829 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
863 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1029 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 348 setOperationAction(ISD::FDIV, VT, Expand);
|