Searched refs:INSN_COND (Results 1 - 3 of 3) sorted by relevance

/external/qemu/tcg/sparc/
H A Dtcg-target.c202 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) macro
219 #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
478 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
482 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
494 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
499 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
554 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
557 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
562 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
574 cc = INSN_COND(tcg_cond_to_bcon
[all...]
/external/valgrind/main/VEX/priv/
H A Dguest_arm_toIR.c11897 # define INSN_COND SLICE_UInt(insn, 31, 28) macro
11902 vassert(BITS4(1,1,1,1) == INSN_COND);
12027 # undef INSN_COND macro
12054 # define INSN_COND SLICE_UInt(insn, 31, 28) macro
12164 switch ( (ARMCondcode)INSN_COND ) {
12181 assign( condT, mk_armg_calculate_condition( INSN_COND ));
12297 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
12338 nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
12364 nCC(INSN_COND), rN, dis_buf );
12395 nCC(INSN_COND), r
14191 # undef INSN_COND macro
[all...]
/external/qemu/tcg/hppa/
H A Dtcg-target.c267 #define INSN_COND(x) ((x) << 13) macro
768 op |= INSN_COND(pacond & 7);
810 op |= INSN_COND(pacond & 7);

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