/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 102 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. 103 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { 104 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 105 if (unsigned N = CSRNum[PhysReg]) 110 /// isReserved - Returns true when PhysReg is a reserved register. 115 bool isReserved(unsigned PhysReg) const { 116 return Reserved.test(PhysReg); 119 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 125 bool isAllocatable(unsigned PhysReg) const { 126 return TRI->isInAllocatableClass(PhysReg) [all...] |
H A D | MachineOperand.h | 454 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 458 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { argument 460 assert(PhysReg < (1u << 30) && "Not a physical register"); 461 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 464 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 465 bool clobbersPhysReg(unsigned PhysReg) const { 466 return clobbersPhysReg(getRegMask(), PhysReg);
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H A D | MachineRegisterInfo.h | 284 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 287 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 423 /// canReserveReg - Returns true if PhysReg can be used as a reserved 426 bool canReserveReg(unsigned PhysReg) const { 427 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
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/external/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 74 << " to " << PrintReg(PhysReg, TRI) << ':'); 76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 77 MRI->setPhysRegUsed(PhysReg); 78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 87 unsigned PhysReg = VRM->getPhys(VirtReg.reg); local 89 << " from " << PrintReg(PhysReg, TRI) << ':'); 91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 100 unsigned PhysReg) { 111 // The BitVector is indexed by PhysReg, no 99 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 117 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 136 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | AllocationOrder.h | 66 /// isHint - Return true if PhysReg is a preferred register. 67 bool isHint(unsigned PhysReg) const { return PhysReg == Hint; }
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H A D | InterferenceCache.h | 39 /// of PhysReg in all basic blocks. 41 /// PhysReg - The register currently represented. 42 unsigned PhysReg; member in class:llvm::InterferenceCache::Entry 63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg. 85 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have 96 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {} 100 PhysReg = 0; 106 unsigned getPhysReg() const { return PhysReg; } 146 // get - Get a valid entry for PhysReg. 147 Entry *get(unsigned PhysReg); 192 setPhysReg(InterferenceCache &Cache, unsigned PhysReg) argument [all...] |
H A D | LiveRegMatrix.h | 87 /// assigned to PhysReg or its aliases. This interference could be resolved 97 /// regmask operand that doesn't preserve PhysReg. This typically means 98 /// VirtReg is live across a call, and PhysReg isn't call-preserved. 102 /// Check for interference before assigning VirtReg to PhysReg. 103 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). 106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 108 /// Assign VirtReg to PhysReg. 110 /// update VirtRegMap. The live range is expected to be available in PhysReg. 111 void assign(LiveInterval &VirtReg, unsigned PhysReg); 113 /// Unassign VirtReg from its PhysReg [all...] |
H A D | RegAllocFast.cpp | 73 unsigned PhysReg; // Currently held here. member in struct:__anon9295::RAFast::LiveReg 78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {} 160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 161 unsigned calcSpillCost(unsigned PhysReg) const; 162 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg); 169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg); 177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 221 if (MO.getReg() == LR.PhysReg) 224 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 231 assert(PhysRegState[LRI->PhysReg] 332 unsigned PhysReg = MO.getReg(); local 390 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument 483 assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) argument 492 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 532 unsigned PhysReg = *I; local 656 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument 730 unsigned PhysReg = LRI->PhysReg; local 753 unsigned PhysReg = LRI->PhysReg; local 1012 unsigned PhysReg = LRI->PhysReg; local 1067 unsigned PhysReg = LRI->PhysReg; local [all...] |
H A D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | RegisterClassInfo.cpp | 89 unsigned PhysReg = RawOrder[i]; local 91 if (Reserved.test(PhysReg)) 93 if (CSRNum[PhysReg]) 94 // PhysReg aliases a CSR, save it for later. 95 CSRAlias.push_back(PhysReg); 97 RCI.Order[N++] = PhysReg;
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H A D | VirtRegMap.cpp | 235 // assigned PhysReg must be marked as live-in to those blocks. 236 unsigned PhysReg = VRM->getPhys(VirtReg); local 237 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); 245 if (!LiveIn[i]->isLiveIn(PhysReg)) 246 LiveIn[i]->addLiveIn(PhysReg); 279 unsigned PhysReg = VRM->getPhys(VirtReg); local 280 assert(PhysReg != VirtRegMap::NO_PHYS_REG && 282 assert(!Reserved.test(PhysReg) && "Reserved register assignment"); 290 SuperKills.push_back(PhysReg); 301 SuperDeads.push_back(PhysReg); [all...] |
H A D | InterferenceCache.cpp | 38 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { argument 39 unsigned E = PhysRegEntries[PhysReg]; 40 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 56 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 57 PhysRegEntries[PhysReg] = E; 71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 82 PhysReg = physReg; 88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 97 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { 168 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { [all...] |
H A D | RegAllocBasic.cpp | 114 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 166 // Spill or split all live virtual registers currently unified under PhysReg 169 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 176 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 188 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << 192 // Spill each interfering vreg allocated to PhysReg or an alias. 230 while (unsigned PhysReg = Order.next()) { 231 // Check for interference in PhysReg 232 switch (Matrix->checkInterference(VirtReg, PhysReg)) { 234 // PhysReg i [all...] |
H A D | RegAllocGreedy.cpp | 183 unsigned PhysReg; member in struct:__anon9299::RAGreedy::GlobalSplitCandidate 188 // Interference for PhysReg. 196 PhysReg = Reg; 216 /// Candidate info for for each PhysReg in AllocationOrder. 442 unsigned PhysReg; local 443 while ((PhysReg = Order.next())) 444 if (!Matrix->checkInterference(VirtReg, PhysReg)) 446 if (!PhysReg || Order.isHint(PhysReg)) 447 return PhysReg; 515 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 586 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &NewVRegs) argument [all...] |
H A D | LiveRangeCalc.h | 109 /// PhysReg, when set, is used to verify live-in lists on basic blocks. 113 unsigned PhysReg); 164 /// PhysReg, when set, is used to verify live-in lists on basic blocks. 165 void extend(LiveInterval *LI, SlotIndex Kill, unsigned PhysReg = 0);
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H A D | LiveRangeCalc.cpp | 136 unsigned PhysReg) { 153 VNInfo *VNI = findReachingDefs(LI, KillMBB, Kill, PhysReg); 177 unsigned PhysReg) { 195 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && 196 !MBB->isLiveIn(PhysReg)) { 134 extend(LiveInterval *LI, SlotIndex Kill, unsigned PhysReg) argument 174 findReachingDefs(LiveInterval *LI, MachineBasicBlock *KillMBB, SlotIndex Kill, unsigned PhysReg) argument
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H A D | MachineRegisterInfo.cpp | 311 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, argument 313 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 316 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 323 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 404 std::string PhysReg; 407 return PhysReg; 412 return PhysReg; 414 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 416 PhysReg += "::"; 417 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 418 return PhysReg; 520 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 521 if (PhysReg.empty()) { 531 PhysRegInputs->push_back(PhysReg); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 113 unsigned &PhysReg, int &Cost) { 126 PhysReg = Reg; 468 unsigned PhysReg = 0; 471 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 472 assert((PhysReg == 0 || !isChain) && 480 PhysReg = 0; 489 OpLatency, PhysReg); 110 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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H A D | SelectionDAGBuilder.cpp | 5822 std::pair<unsigned, const TargetRegisterClass*> PhysReg = local 5832 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5836 EVT RegVT = *PhysReg.second->vt_begin(); 5862 if (unsigned AssignedReg = PhysReg.first) { 5863 const TargetRegisterClass *RC = PhysReg.second; 5895 if (const TargetRegisterClass *RC = PhysReg.second) {
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