Searched refs:RHS1 (Results 1 - 3 of 3) sorted by relevance

/external/llvm/include/llvm/ADT/
H A DSparseBitVector.h249 // RHS1 & ~RHS2 into this element
250 void intersectWithComplement(const SparseBitVectorElement &RHS1,
257 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
677 // Result of RHS1 & ~RHS2 is stored into this bitmap.
678 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1,
683 ElementListConstIter Iter1 = RHS1.Elements.begin();
686 // If RHS1 is empty, we are done
687 // If RHS2 is empty, we still have to copy RHS1
688 if (RHS1.Elements.empty())
693 if (Iter1 == RHS1
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/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3040 SDValue RHS1, RHS2; local
3042 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3048 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
6831 unsigned RHS1 = MI->getOperand(3).getReg(); local
6835 .addReg(LHS1).addReg(RHS1));
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8743 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); local
8750 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
10612 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); local
10619 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),

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