Searched refs:SPR (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/Target/PowerPC/
H A DPPCJITInfo.cpp36 #define BUILD_MTSPR(RS,SPR) \
37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
/external/qemu/tcg/ppc/
H A Dtcg-target.c384 #define SPR(a,b) ((((a)<<5)|(b))<<11) macro
385 #define LR SPR(8, 0)
386 #define CTR SPR(9, 0)
/external/qemu/tcg/ppc64/
H A Dtcg-target.c376 #define SPR(a,b) ((((a)<<5)|(b))<<11) macro
377 #define LR SPR(8, 0)
378 #define CTR SPR(9, 0)
/external/valgrind/main/VEX/priv/
H A Dguest_ppc_toIR.c6272 UInt SPR = b11to20; local
6285 /* Reorder SPR field as per PPC32 p470 */
6286 SPR = ((SPR & 0x1F) << 5) | ((SPR >> 5) & 0x1F);
6338 switch (SPR) { // Choose a register...
6367 UInt arg = SPR==268 ? 0 : 1;
6382 DIP("mfspr r%u,%u", rD_addr, (UInt)SPR);
6403 DIP("mfspr r%u,%u", rD_addr, (UInt)SPR);
6408 vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(
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/external/qemu/
H A Dppc-dis.c778 /* The SPR field in an XFX form instruction. This is flipped--the
780 #define SPR SISIGNOPT + 1
781 #define PMR SPR
786 #define SPRBAT SPR + 1
806 /* The TBR field in an XFX form instruction. This is like the SPR
1498 /* The SPR field in an XFX form instruction. This is flipped--the
1559 /* The TBR field in an XFX instruction. This is just like SPR, but it
1879 /* An XFX form instruction with the SPR field filled in. */
1884 /* An XFX form instruction with the SPR field filled in except for the
1888 /* An XFX form instruction with the SPR fiel
776 #define SPR macro
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