| /external/easymock/src/org/easymock/internal/ |
| H A D | Range.java | 24 private final int minimum;
field in class:Range
32 public Range(int minimum, int maximum) {
argument
33 if (!(minimum <= maximum)) {
35 "minimum must be <= maximum"));
38 if (!(minimum >= 0)) {
40 "minimum must be >= 0"));
47 this.minimum = minimum;
52 return minimum == maximum;
60 return minimum;
[all...] |
| /external/webkit/Source/WebCore/html/ |
| H A D | StepRange.h | 36 double minimum; member in class:WebCore::StepRange
37 double maximum; // maximum must be >= minimum.
46 return clampValue((minimum + maximum) / 2);
52 if (minimum == maximum)
55 return (value - minimum) / (maximum - minimum);
61 return minimum + proportion * (maximum - minimum);
|
| H A D | StepRange.cpp | 45 minimum = element->minimum();
50 double clampedValue = max(minimum, min(value, maximum));
53 // Rounds clampedValue to minimum + N * step.
54 clampedValue = minimum + round((clampedValue - minimum) / step) * step;
57 ASSERT(clampedValue >= minimum);
67 value = (minimum + maximum) / 2;
76 oldValue = (minimum + maximum) / 2;
|
| /external/oprofile/events/mips/5K/ |
| H A D | events | 8 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
9 event:0x2 counters:0,1 um:zero minimum:500 name:LOADS_EXECED : Load/pref(x)/sync/cache-ops executed
10 event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed
11 event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed
16 event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched
17 event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores
18 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_EXECED : Branches executed
19 event:0x7 counters:0 um:zero minimum:500 name:ITLB_MISSES : ITLB miss
20 event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss
21 event:0x9 counters:0 um:zero minimum
[all...] |
| /external/oprofile/events/mips/34K/ |
| H A D | events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum
[all...] |
| /external/oprofile/events/i386/atom/ |
| H A D | events | 5 event:0x3c counters:0,1 um:cpu_clk_unhalted minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
6 event:0x3c counters:0,1 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
7 event:0xc0 counters:0,1 um:one minimum:6000 name:INST_RETIRED : number of instructions retired
8 event:0x2e counters:0,1 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
9 event:0x2e counters:0,1 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
10 event:0xc4 counters:0,1 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
11 event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
13 event:0x02 counters:0,1 um:store_forwards minimum:6000 name:STORE_FORWARDS : Good store forwards
14 event:0x06 counters:0,1 um:segment_reg_loads minimum:6000 name:SEGMENT_REG_LOADS : Number of segment register loads
15 event:0x07 counters:0,1 um:simd_prefetch minimum
[all...] |
| /external/oprofile/events/mips/sb1/ |
| H A D | events | 5 event:0x10 counters:0,1,2,3 um:zero minimum:500 name:CYCLES :Elapsed cycles
8 event:0x28 counters:1,2,3 um:zero minimum:500 name:ISSUE_L0 :Issue to L0
9 event:0x29 counters:1,2,3 um:zero minimum:500 name:ISSUE_L1 :Issue to L0
10 event:0x2a counters:1,2,3 um:zero minimum:500 name:ISSUE_E0 :Issue to E0
11 event:0x2b counters:1,2,3 um:zero minimum:500 name:ISSUE_E1 :Issue to E1
14 event:0x2f counters:1,2,3 um:zero minimum:500 name:BRANCH_MISSPREDICTS :Branch mispredicts
15 event:0x1d counters:1,2,3 um:zero minimum:500 name:MBOX_REPLAY :MBOX replay
16 event:0x1c counters:1,2,3 um:zero minimum:500 name:DCFIFO :DCFIFO
17 event:0x1e counters:1,2,3 um:zero minimum:500 name:DATA_DEPENDENCY_REPLAY :Data dependency replay
18 event:0x1b counters:1,2,3 um:zero minimum
[all...] |
| /external/oprofile/events/mips/r10000/ |
| H A D | events | 6 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
7 event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
8 event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
9 event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
10 event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
11 event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
12 event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
13 event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued
14 event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated
15 event:0x05 counters:0 um:zero minimum
[all...] |
| /external/oprofile/events/mips/r12000/ |
| H A D | events | 4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
5 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
6 event:0x2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads
7 event:0x3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores
8 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy
9 event:0x5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
10 event:0x6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches
11 event:0x7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache
12 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data
13 event:0x9 counters:0,1,2,3 um:zero minimum
[all...] |
| /external/oprofile/events/mips/rm7000/ |
| H A D | events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued
6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
7 event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued
8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
10 event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs
11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
12 event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
13 event:0x09 counters:0,1 um:zero minimum
[all...] |
| /external/oprofile/events/mips/24K/ |
| H A D | events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum
[all...] |
| /external/oprofile/events/mips/vr5432/ |
| H A D | events | 4 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
5 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
6 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
7 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
8 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
9 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
10 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
11 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
12 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
13 event:0x9 counters:0,1 um:zero minimum
[all...] |
| /external/oprofile/events/mips/vr5500/ |
| H A D | events | 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
7 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
8 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
9 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction
10 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction
11 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction
12 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory
13 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
14 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss
15 event:0x9 counters:0,1 um:zero minimum
[all...] |
| /external/oprofile/events/x86-64/family11h/ |
| H A D | events | 24 event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
25 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
26 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
29 event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
30 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
31 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
32 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
33 event:0x24 counters:0,1,2,3 um:locked_ops minimum:500 name:LOCKED_OPS : Locked operations
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum
[all...] |
| /external/oprofile/events/x86-64/hammer/ |
| H A D | events | 22 event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
24 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
27 event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
28 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
29 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
31 event:0x24 counters:0,1,2,3 um:locked_ops minimum:500 name:LOCKED_OPS : Locked operations
34 event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions
35 event:0x27 counters:0,1,2,3 um:zero minimum
[all...] |
| /external/oprofile/events/mips/rm9000/ |
| H A D | events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
7 event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued
8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
10 event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs
11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions
12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
13 event:0x0a counters:0,1 um:zero minimum
[all...] |
| /external/oprofile/events/mips/1004K/ |
| H A D | events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum
[all...] |
| /external/oprofile/events/mips/20K/ |
| H A D | events | 6 event:0x0 counters:0 um:zero minimum:500 name:CYCLES : CPU cycles
7 event:0x1 counters:0 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0 um:zero minimum:500 name:FETCH_GROUPS : Fetch groups entering CPU execution pipes
9 event:0x3 counters:0 um:zero minimum:500 name:FP_INSNS_COMPLETED : Instructions completed in FPU datapath (computational event:instructions only)
10 event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions
11 event:0x5 counters:0 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution
12 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution
13 event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions
14 event:0x8 counters:0 um:zero minimum:500 name:REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH : Replays due to load-dependent speculative dispatch
15 event:0x9 counters:0 um:zero minimum
[all...] |
| /external/oprofile/events/mips/25K/ |
| H A D | events | 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles
7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued
13 event:0x7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs
14 event:0x8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception)
15 event:0x9 counters:0,1 um:zero minimum
[all...] |
| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/asn1/x509/ |
| H A D | GeneralSubtree.java | 23 * minimum [0] BaseDistance DEFAULT 0,
38 private ASN1Integer minimum; field in class:GeneralSubtree
56 minimum = ASN1Integer.getInstance(o, false);
72 throw new IllegalArgumentException("Bad tag number for 'minimum': " + oMin.getTagNo());
74 minimum = ASN1Integer.getInstance(oMin, false);
97 * According RFC 3280, the minimum and maximum fields are not used with any
98 * name forms, thus minimum MUST be zero, and maximum MUST be absent.
100 * If minimum is <code>null</code>, zero is assumed, if
105 * @param minimum
113 BigInteger minimum,
111 GeneralSubtree( GeneralName base, BigInteger minimum, BigInteger maximum) argument
[all...] |
| /external/oprofile/events/i386/westmere/ |
| H A D | events | 6 # Note the minimum counts are not discovered experimentally and could be likely
10 event:0x03 counters:0,1,2,3 um:x02 minimum:200000 name:LOAD_BLOCK : Loads that partially overlap an earlier store
11 event:0x04 counters:0,1,2,3 um:x07 minimum:200000 name:SB_DRAIN : All Store buffer stall cycles
12 event:0x05 counters:0,1,2,3 um:x02 minimum:200000 name:MISALIGN_MEM_REF : Misaligned store references
13 event:0x06 counters:0,1,2,3 um:store_blocks minimum:200000 name:STORE_BLOCKS : Loads delayed with at-Retirement block code
14 event:0x07 counters:0,1,2,3 um:x01 minimum:200000 name:PARTIAL_ADDRESS_ALIAS : False dependencies due to partial address aliasing
15 event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:200000 name:DTLB_LOAD_MISSES : DTLB load misses
16 event:0x0b counters:0,1,2,3 um:mem_inst_retired minimum:2000000 name:MEM_INST_RETIRED : Memory instructions retired above 0 clocks (Precise Event)
17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
18 event:0x0e counters:0,1,2,3 um:uops_issued minimum
[all...] |
| /external/oprofile/events/mips/74K/ |
| H A D | events | 14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
20 event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
29 event:0xb counters:0,2 um:zero minimum
[all...] |
| /external/oprofile/events/i386/nehalem/ |
| H A D | events | 7 # Note the minimum counts are not discovered experimentally and could be likely
10 event:0x3c counters:0,1,2,3 um:zero minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
11 event:0x3c counters:0,1,2,2 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
12 event:0x2e counters:0,1,2,3 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
13 event:0x2e counters:0,1,2,3 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
14 event:0xc0 counters:0,1,2,3 um:inst_retired minimum:6000 name:INST_RETIRED : number of instructions retired
15 event:0xc4 counters:0,1,2,3 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
16 event:0xc5 counters:0,1,2,3 um:br_misp_retired minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
18 event:0x02 counters:0,1,2,3 um:sb_forward minimum:6000 name:SB_FORWARD : Counts the number of store forwards.
19 event:0x03 counters:0,1,2,3 um:load_block minimum
[all...] |
| /external/wpa_supplicant_8/wpa_supplicant/wpa_gui-qt4/ |
| H A D | signalbar.cpp | 43 opts.minimum = -95;
45 if (signal < opts.minimum)
46 opts.progress = opts.minimum;
|
| /external/proguard/src/proguard/ |
| H A D | UpToDateChecker.java | 120 * Returns the minimum or maximum modification time of the given file or
123 private long lastModified(File file, boolean minimum) argument
133 long lastModified = files.length != 0 && minimum ?
138 long fileLastModified = lastModified(files[index], minimum);
139 if ((lastModified < fileLastModified) ^ minimum)
|