Searched refs:virtReg (Results 1 - 3 of 3) sorted by relevance

/external/llvm/lib/CodeGen/
H A DVirtRegMap.h92 bool hasPhys(unsigned virtReg) const {
93 return getPhys(virtReg) != NO_PHYS_REG;
98 unsigned getPhys(unsigned virtReg) const {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 return Virt2PhysMap[virtReg];
105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) { argument
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
111 Virt2PhysMap[virtReg] = physReg;
116 void clearVirt(unsigned virtReg) { argument
138 setIsSplitFromReg(unsigned virtReg, unsigned SReg) argument
[all...]
H A DVirtRegMap.cpp79 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) { argument
80 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
90 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { argument
91 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
92 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
94 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
95 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
98 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { argument
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 assert(Virt2StackSlotMap[virtReg]
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H A DLiveIntervalUnion.h150 LiveInterval &virtReg() const { function in class:llvm::LiveIntervalUnion::Query

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