Searched refs:bit (Results 1 - 25 of 25) sorted by relevance

/dalvik/dexgen/src/com/android/dexgen/util/
H A DBits.java20 * Utilities for treating {@code int[]}s as bit sets.
31 * Constructs a bit set to contain bits up to the given index (exclusive).
33 * @param max {@code >= 0;} the maximum bit index (exclusive)
42 * Gets the maximum index (exclusive) for the given bit set.
44 * @param bits {@code non-null;} bit set in question
52 * Gets the value of the bit at the given index.
54 * @param bits {@code non-null;} bit set to operate on
55 * @param idx {@code >= 0, < getMax(set);} which bit
56 * @return the value of the indicated bit
60 int bit
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/dalvik/dx/src/com/android/dx/util/
H A DBits.java20 * Utilities for treating {@code int[]}s as bit sets.
31 * Constructs a bit set to contain bits up to the given index (exclusive).
33 * @param max {@code >= 0;} the maximum bit index (exclusive)
42 * Gets the maximum index (exclusive) for the given bit set.
44 * @param bits {@code non-null;} bit set in question
52 * Gets the value of the bit at the given index.
54 * @param bits {@code non-null;} bit set to operate on
55 * @param idx {@code >= 0, < getMax(set);} which bit
56 * @return the value of the indicated bit
60 int bit
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/dalvik/vm/compiler/template/armv5te/
H A DTEMPLATE_CMPL_DOUBLE.S27 @ Test for NaN with a second comparison. EABI forbids testing bit
H A DTEMPLATE_CMPL_FLOAT.S45 @ Test for NaN with a second comparison. EABI forbids testing bit
/dalvik/vm/compiler/template/mips/
H A Dfbinop.S3 * Generic 32-bit binary float operation. a0 = a1 op a2.
31 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0
/dalvik/vm/alloc/TEST/HeapBitmapTest/
H A Dmain.c211 unsigned long bit; local
219 bit = dvmHeapBitmapSetAndReturnObjectBit(&hb, HEAP_BASE);
220 assert(bit == 0);
239 bit = dvmHeapBitmapSetAndReturnObjectBit(&hb, HEAP_BASE);
240 assert(bit != 0);
259 bit = dvmHeapBitmapSetAndReturnObjectBit(&hb,
261 assert(bit == 0);
280 bit = dvmHeapBitmapSetAndReturnObjectBit(&hb,
282 assert(bit != 0);
/dalvik/vm/
H A DBitVector.cpp18 * Implementation of an expandable bit vector.
29 * Allocate a bit vector with enough space to hold at least the specified
37 assert(sizeof(bv->storage[0]) == 4); /* assuming 32-bit units */
62 * "Allocate" the first-available bit in the bitmap.
70 unsigned int word, bit; local
78 bit = ffs(~(pBits->storage[word])) -1;
79 assert(bit < 32);
80 pBits->storage[word] |= 1 << bit;
81 return (word << 5) | bit;
100 * Mark the specified bit a
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/dalvik/vm/arch/arm/
H A DCallEABI.S48 We receive a collection of 32-bit values which correspond to arguments from
76 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
77 64-bit quantities (long long, double) must be 64-bit aligned. This means
92 * r3 argc (number of 32-bit values in argv)
100 * argInfo (32-bit int) layout:
128 * On entry to a function, "sp" must be 64-bit aligned. This means
158 @.pad #4 @ adjust for 64-bit align
161 @ Ensure 64-bit alignment. EABI guarantees sp is aligned on entry, make
163 DBG tst sp, #4 @ 64-bit aligne
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/dalvik/vm/mterp/mips/
H A Dbinflop.S3 * Generic 32-bit binary float operation.
27 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0
H A DOP_IGET_WIDE.S8 * Wide 32-bit instance field get.
40 vLOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok)
42 LOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok)
H A DOP_IGET_WIDE_JUMBO.S8 * Jumbo 64-bit instance field get.
47 vLOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok)
49 LOAD64(a0, a1, rOBJ) # a0/a1 <- obj.field (64-bit align ok)
/dalvik/vm/mterp/armv6t2/
H A DOP_IGET_WIDE.S7 * Wide 32-bit instance field get.
36 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
/dalvik/vm/mterp/armv5te/
H A DOP_EXECUTE_INLINE.S24 sub sp, sp, #8 @ make room for arg, +64 bit align
80 sub sp, sp, #8 @ make room for arg, +64 bit align
H A DOP_EXECUTE_INLINE_RANGE.S22 sub sp, sp, #8 @ make room for arg, +64 bit align
73 sub sp, sp, #8 @ make room for arg, +64 bit align
H A DOP_IGET_WIDE.S8 * Wide 32-bit instance field get.
41 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
H A Dfooter.S217 * the following 32-bit word contains the target rPC value.
218 * Note that lr (r14) will have its low-order bit set to denote
1066 * registers for EABI 64-bit stack alignment.)
1119 * Print the 32-bit quantity in r0 as a hex value, preserving registers.
1134 * Print the 64-bit quantity in r0-r1, preserving registers.
1181 mvn r1, r1 @ bit-invert mask
/dalvik/vm/analysis/
H A DRegisterMap.cpp158 ALOGI("Register Map bit difference stats:");
366 * Given a line of registers, output a bit vector that indicates whether
371 * in the low bit of the first byte.
382 val |= 0x80; /* set hi bit */
537 ALOGE("GLITCH: addr %d reg %d: bit=%d reg=%d(%d)",
560 * Advance "ptr" to ensure 32-bit alignment.
766 /* a bit late */
1100 Each entry consists of an address and a bit vector. Adjacent entries are
1105 bit vectors. However, the register values at a given address do not
1116 change the bit vecto
1313 int prev, cur, bit; local
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/dalvik/libdex/
H A DDexSwapVerify.cpp257 * Set the given bit in pDefinedClassBits, returning its former value.
261 u4 bit = 1 << (typeIdx & 0x1f); local
263 bool result = (*element & bit) != 0;
265 *element |= bit;
342 * one-bit-on integer, suitable for use in an int-sized bit set.
401 u4 usedBits = 0; // Bit set: one bit per section
448 u4 bit = mapTypeToBitMask(item->type); local
450 if (bit == 0) {
454 if ((usedBits & bit) !
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/dalvik/vm/compiler/template/out/
H A DCompilerTemplateAsm-armv5te.S54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
72 r7 rINST first 16-bit code unit of current instruction
124 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
141 * in the worst case (the 64-bit values are equal).
525 @ Test for NaN with a second comparison. EABI forbids testing bit
569 @ Test for NaN with a second comparison. EABI forbids testing bit
631 @ Test for NaN with a second comparison. EABI forbids testing bit
693 @ Test for NaN with a second comparison. EABI forbids testing bit
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/dalvik/vm/mterp/out/
H A DInterpAsm-armv5te-vfp.S54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
67 r7 rINST first 16-bit code unit of current instruction
117 * to point to the next instruction. "_count" is in 16-bit code units.
139 * in bytes, *not* 16-bit code units, and may be a signed value.
150 * "_count" value is in 16-bit code units. Does not advance rPC.
184 * Get/set the 32-bit value from a Dalvik register.
585 * Return a 32-bit value. Copies the return value into the "thread"
601 * Return a 64-bit valu
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H A DInterpAsm-armv7-a-neon.S54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
67 r7 rINST first 16-bit code unit of current instruction
117 * to point to the next instruction. "_count" is in 16-bit code units.
139 * in bytes, *not* 16-bit code units, and may be a signed value.
150 * "_count" value is in 16-bit code units. Does not advance rPC.
184 * Get/set the 32-bit value from a Dalvik register.
597 * Return a 32-bit value. Copies the return value into the "thread"
613 * Return a 64-bit valu
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H A DInterpAsm-armv7-a.S54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
67 r7 rINST first 16-bit code unit of current instruction
117 * to point to the next instruction. "_count" is in 16-bit code units.
139 * in bytes, *not* 16-bit code units, and may be a signed value.
150 * "_count" value is in 16-bit code units. Does not advance rPC.
184 * Get/set the 32-bit value from a Dalvik register.
597 * Return a 32-bit value. Copies the return value into the "thread"
613 * Return a 64-bit valu
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H A DInterpAsm-armv5te.S54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
67 r7 rINST first 16-bit code unit of current instruction
117 * to point to the next instruction. "_count" is in 16-bit code units.
139 * in bytes, *not* 16-bit code units, and may be a signed value.
150 * "_count" value is in 16-bit code units. Does not advance rPC.
184 * Get/set the 32-bit value from a Dalvik register.
585 * Return a 32-bit value. Copies the return value into the "thread"
601 * Return a 64-bit valu
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H A DInterpAsm-mips.S30 s4 rINST first 16-bit code unit of current instruction
731 * Return a 32-bit value. Copies the return value into the "thread"
748 * Return a 64-bit value. Copies the return value into the "thread"
766 * Return a 32-bit value. Copies the return value into the "thread"
1343 * Unconditional branch, 8-bit offset.
1369 * Unconditional branch, 16-bit offset.
1393 * Unconditional branch, 32-bit offset.
1734 * Compare two 64-bit values
2333 * Arrays of long/double are 64-bit aligned.
2574 * Arrays of long/double are 64-bit aligne
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H A DInterpAsm-x86.S24 * 32-bit x86 definitions and declarations.
35 32-bit in eax
36 64-bit in edx:eax (low-order 32 in eax)
63 rINSTw bx first 16-bit code of current instruction
248 * Get/set the 32-bit value from a Dalvik register.
528 * Return a 32-bit value. Copies the return value into the "self"
543 * Return a 64-bit value. Copies the return value into the "self"
559 * Return a 32-bit value. Copies the return value into the "self"
1483 * Unconditional branch, 8-bit offset.
1505 * Unconditional branch, 16-bit offse
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