Searched refs:operands (Results 1 - 25 of 25) sorted by path

/dalvik/dx/src/com/android/dx/ssa/
H A DPhiInsn.java41 * {@code non-null;} operands of the instruction; built up by
44 private final ArrayList<Operand> operands = new ArrayList<Operand>(); field in class:PhiInsn
50 * Constructs a new phi insn with no operands.
82 * Updates the TypeBearers of all the sources (phi operands) to be
86 * Note that local association of operands are preserved in this step.
91 for (Operand o : operands) {
130 operands.add(new Operand(registerSpec, predBlock.getIndex(),
144 for (Operand o : operands) {
150 operands.removeAll(operandsToRemove);
164 return operands
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/dalvik/vm/compiler/codegen/arm/
H A DArchUtility.cpp96 operand = lir->operands[nc-'0'];
204 int offset_1 = lir->operands[0];
205 int offset_2 = NEXT_LIR(lir)->operands[0];
301 int dest = lir->operands[0];
348 (char *) lir->operands[1]);
359 lir->operands[1]);
412 ((CallsiteInfo *) armLIR->operands[0])->classDescriptor);
419 armLIR->operands[0]);
H A DArmLIR.h49 * r0, r1, r2, r3 to hold operands/results
53 * r0, r1, r2, r3, r8, r9, r10, r11, r12, r14 for operands/results
55 * s16-s31/d8-d15 for operands/results
766 int operands[4]; // [0..3] = [dest, src1, src2, extra] member in struct:ArmLIR
H A DAssemble.cpp39 * operands: number of operands (for sanity check purposes)
53 * 0 -> operands[0] (dest)
54 * 1 -> operands[1] (src1)
55 * 2 -> operands[2] (src2)
56 * 3 -> operands[3] (extra)
916 *dataPtr++ = dataLIR->operands[0];
921 *dataPtr++ = dataLIR->operands[0];
942 (lir->operands[0] == 1)) {
955 ((lir->opcode == kThumb2Vldrs) && (lir->operands[
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H A DCodegenCommon.cpp84 if (DOUBLEREG(lir->operands[0])) {
154 setupRegMask(&lir->defMask, lir->operands[0]);
158 setupRegMask(&lir->defMask, lir->operands[1]);
170 lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
174 lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
191 setupRegMask(&lir->useMask, lir->operands[i]);
205 lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
209 lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
250 setupRegMask(&lir->useMask, lir->operands[i]);
262 * operands
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H A DCodegenDriver.cpp213 insn->operands[0] = dest;
214 insn->operands[1] = src1;
903 /* Deduce sizes of operands */
977 pcrLabel->operands[0] = dPC;
978 pcrLabel->operands[1] = mir->offset;
1199 * For verbose printing, store the method pointer in operands[1] first as
1200 * operands[0] will be clobbered in dvmCompilerMIR2LIR.
1202 predChainingCell->operands[1] = (int) mir->meta.callsiteInfo->method;
1233 pcrLabel->operands[0] = dPC;
1234 pcrLabel->operands[
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H A DLocalOptimizations.cpp24 /* Check RAW, WAR, and WAR dependency on the register operands */
108 int nativeRegId = thisLIR->operands[0];
160 REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)){
165 if (checkLIR->operands[0] != nativeRegId) {
167 checkLIR->operands[0],
177 REGTYPE(checkLIR->operands[0]) ==
187 if (checkLIR->operands[0] !=
191 checkLIR->operands[0],
234 * their register operands have any RAW, WAR, and WAW
/dalvik/vm/compiler/codegen/arm/Thumb/
H A DFactory.cpp79 loadPcRel->operands[0] = tDest;
82 loadPcRel->aliasInfo = dataTarget->operands[0];
90 if (dataTarget->operands[0] != value) {
91 newLIR2(cUnit, kThumbAddRI8, tDest, value - dataTarget->operands[0]);
134 loadPcRel->operands[0] = rDest;
137 loadPcRel->aliasInfo = dataTarget->operands[0];
853 res->operands[0] = rDest;
854 res->operands[1] = rSrc;
908 pushFP->operands[0] = 1 << r5FP;
915 pushLR->operands[
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/dalvik/vm/compiler/codegen/arm/Thumb2/
H A DFactory.cpp66 loadPcRel->operands[0] = rDest;
67 loadPcRel->operands[1] = r15pc;
70 loadPcRel->aliasInfo = dataTarget->operands[0];
174 loadPcRel->operands[0] = rDest;
177 loadPcRel->aliasInfo = dataTarget->operands[0];
185 if (dataTarget->operands[0] != value) {
186 opRegImm(cUnit, kOpAdd, rDest, value - dataTarget->operands[0]);
225 loadPcRel->operands[0] = rDest;
228 loadPcRel->aliasInfo = dataTarget->operands[0];
1162 res->operands[
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/dalvik/vm/compiler/codegen/arm/armv7-a-neon/
H A DMethodCodegenDriver.cpp249 labelList[blockId].operands[0] = bb->startOffset;
/dalvik/vm/compiler/codegen/mips/
H A DArchUtility.cpp53 operand = lir->operands[nc-'0'];
127 int offset_1 = lir->operands[0];
128 int offset_2 = NEXT_LIR(lir)->operands[0];
224 int dest = lir->operands[0];
270 (char *) lir->operands[1]);
281 lir->operands[1]);
334 ((CallsiteInfo *) mipsLIR->operands[0])->classDescriptor);
341 mipsLIR->operands[0]);
H A DAssemble.cpp40 * operands: number of operands (for sanity check purposes)
54 * 0 -> operands[0] (dest)
55 * 1 -> operands[1] (src1)
56 * 2 -> operands[2] (src2)
57 * 3 -> operands[3] (extra)
420 *dataPtr++ = dataLIR->operands[0];
425 *dataPtr++ = dataLIR->operands[0];
465 lir->operands[0] = delta >> 2;
479 lir->operands[
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H A DCodegenCommon.cpp87 if (DOUBLEREG(lir->operands[0])) {
172 setupRegMask(&lir->defMask, lir->operands[0]);
176 setupRegMask(&lir->defMask, lir->operands[1]);
188 lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
192 lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
209 setupRegMask(&lir->useMask, lir->operands[i]);
223 lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
227 lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
258 setupRegMask(&lir->useMask, lir->operands[i]);
270 * operands
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H A DCodegenDriver.cpp278 insn->operands[0] = dest;
279 insn->operands[1] = src1;
940 /* Deduce sizes of operands */
1014 pcrLabel->operands[0] = dPC;
1015 pcrLabel->operands[1] = mir->offset;
1248 * For verbose printing, store the method pointer in operands[1] first as
1249 * operands[0] will be clobbered in dvmCompilerMIR2LIR.
1251 predChainingCell->operands[1] = (int) mir->meta.callsiteInfo->method;
1286 pcrLabel->operands[0] = dPC;
1287 pcrLabel->operands[
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H A DGlobalOptimizations.cpp163 savedLIR[i]->useMask &= ~(1 << thisLIR->operands[0]);
164 savedLIR[i]->useMask |= 1 << thisLIR->operands[1];
166 savedLIR[i]->operands[0] == thisLIR->operands[0])
167 savedLIR[i]->operands[0] = thisLIR->operands[1];
169 savedLIR[i]->operands[1] == thisLIR->operands[0])
170 savedLIR[i]->operands[1] = thisLIR->operands[
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H A DLocalOptimizations.cpp24 /* Check RAW, WAR, and WAR dependency on the register operands */
108 int nativeRegId = thisLIR->operands[0];
160 REGTYPE(checkLIR->operands[0]) == REGTYPE(nativeRegId)){
165 if (checkLIR->operands[0] != nativeRegId) {
167 checkLIR->operands[0],
177 REGTYPE(checkLIR->operands[0]) ==
187 if (checkLIR->operands[0] !=
191 checkLIR->operands[0],
234 * their register operands have any RAW, WAR, and WAW
H A DMipsLIR.h54 * a0-a3 to hold operands
606 int operands[4]; // [0..3] = [dest, src1, src2, extra] member in struct:MipsLIR
/dalvik/vm/compiler/codegen/mips/Mips32/
H A DFactory.cpp49 res->operands[0] = rDest;
50 res->operands[1] = rSrc;
63 /* note the operands are swapped for the mtc1 instr */
65 res->operands[0] = rSrc;
66 res->operands[1] = rDest;
846 res->operands[0] = rDest;
847 res->operands[1] = rSrc;
875 /* note the operands are swapped for the mtc1 instr */
975 pushFP->operands[0] = 1 << r5FP;
982 pushLR->operands[
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/dalvik/vm/compiler/codegen/x86/
H A DCodegenInterface.cpp756 loadConstant(cUnit, r0, pcrLabel[i]->operands[0]);
1175 //labelList[i].operands[0] = labelList[i].operands[1];
/dalvik/vm/compiler/codegen/x86/libenc/
H A Ddec_base.cpp200 EncoderBase::Operand& opnd = pinst->operands[pinst->argc];
218 EncoderBase::Operand& regOpnd = pinst->operands[pinst->argc];
223 EncoderBase::Operand& regOpnd = pinst->operands[pinst->argc];
242 // disassembler doesn't require to parse all operands
459 EncoderBase::Operand& opnd = pinst->operands[pinst->argc];
H A Ddec_base.h103 EncoderBase::Operand operands[3]; member in struct:Inst
H A Denc_base.cpp185 // of the operands is ST(i) from the FPU register stack. The
396 const EncoderBase::Operand& decoded = inst.operands[i];
725 // must match only for def operands, and dont care about use ones
H A Denc_wrapper.cpp113 //TODO: the order of operands
127 printOperand(decInst.operands[decInst.argc-1-k]);
187 add_imm(args, decInst.operands[0].size(), imm, true/*is_signed*/);
223 //both operands have same size
366 args.add(decInst.operands[0]);
367 add_imm(args, decInst.operands[1].size(), imm, true/*is_signed*/);
435 //a single operand or 2 operands?
539 sz += DisassembleOperandToBuf(decInst.operands[decInst.argc-1],
543 sz += DisassembleOperandToBuf(decInst.operands[k], &strbuf[sz], len-sz);
/dalvik/vm/compiler/template/armv5te/
H A DTEMPLATE_CMPL_DOUBLE.S10 * on what value we'd like to return when one of the operands is NaN.
17 push {r0-r3} @ save operands
24 add sp, #16 @ drop unused operands
31 pop {r2-r3} @ restore operands in reverse order
32 pop {r0-r1} @ restore operands in reverse order
/dalvik/vm/compiler/template/out/
H A DCompilerTemplateAsm-armv5te.S508 * on what value we'd like to return when one of the operands is NaN.
515 push {r0-r3} @ save operands
522 add sp, #16 @ drop unused operands
529 pop {r2-r3} @ restore operands in reverse order
530 pop {r0-r1} @ restore operands in reverse order
552 * on what value we'd like to return when one of the operands is NaN.
559 push {r0-r3} @ save operands
566 add sp, #16 @ drop unused operands
573 pop {r2-r3} @ restore operands in reverse order
574 pop {r0-r1} @ restore operands i
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