Searched refs:imm (Results 1 - 25 of 82) sorted by relevance

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/external/webkit/Source/JavaScriptCore/assembler/
H A DARMAssembler.cpp54 ARMWord ARMAssembler::getOp2(ARMWord imm) argument
58 if (imm <= 0xff)
59 return OP2_IMM | imm;
61 if ((imm & 0xff000000) == 0) {
62 imm <<= 8;
66 imm = (imm << 24) | (imm >> 8);
70 if ((imm & 0xff000000) == 0) {
71 imm <<
91 genInt(int reg, ARMWord imm, bool positive) argument
200 getImm(ARMWord imm, int tmpReg, bool invert) argument
220 moveImm(ARMWord imm, int dest) argument
240 encodeComplexImm(ARMWord imm, int dest) argument
[all...]
H A DMacroAssembler.h101 void poke(TrustedImmPtr imm, int index = 0) argument
103 storePtr(imm, Address(stackPointerRegister, (index * sizeof(void*))));
108 void branchPtr(Condition cond, RegisterID op1, TrustedImmPtr imm, Label target) argument
110 branchPtr(cond, op1, imm).linkTo(target, this);
118 void branch32(Condition cond, RegisterID op1, TrustedImm32 imm, Label target) argument
120 branch32(cond, op1, imm).linkTo(target, this);
153 void addPtr(TrustedImm32 imm, RegisterID srcDest) argument
155 add32(imm, srcDest);
158 void addPtr(TrustedImmPtr imm, RegisterID dest) argument
160 add32(TrustedImm32(imm), des
163 addPtr(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
173 andPtr(TrustedImm32 imm, RegisterID srcDest) argument
183 orPtr(TrustedImmPtr imm, RegisterID dest) argument
188 orPtr(TrustedImm32 imm, RegisterID dest) argument
198 subPtr(TrustedImm32 imm, RegisterID dest) argument
203 subPtr(TrustedImmPtr imm, RegisterID dest) argument
213 xorPtr(TrustedImm32 imm, RegisterID srcDest) argument
259 storePtr(TrustedImmPtr imm, ImplicitAddress address) argument
264 storePtr(TrustedImmPtr imm, void* address) argument
336 branchSubPtr(Condition cond, TrustedImm32 imm, RegisterID dest) argument
[all...]
H A DX86Assembler.h286 void push_i32(int imm) argument
289 m_formatter.immediate32(imm);
305 void adcl_im(int imm, const void* addr) argument
307 if (CAN_SIGN_EXTEND_8_32(imm)) {
309 m_formatter.immediate8(imm);
312 m_formatter.immediate32(imm);
332 void addl_ir(int imm, RegisterID dst) argument
334 if (CAN_SIGN_EXTEND_8_32(imm)) {
336 m_formatter.immediate8(imm);
339 m_formatter.immediate32(imm);
343 addl_im(int imm, int offset, RegisterID base) argument
360 addq_ir(int imm, RegisterID dst) argument
371 addq_im(int imm, int offset, RegisterID base) argument
382 addl_im(int imm, const void* addr) argument
409 andl_ir(int imm, RegisterID dst) argument
420 andl_im(int imm, int offset, RegisterID base) argument
437 andq_ir(int imm, RegisterID dst) argument
448 andl_im(int imm, const void* addr) argument
495 orl_ir(int imm, RegisterID dst) argument
506 orl_im(int imm, int offset, RegisterID base) argument
523 orq_ir(int imm, RegisterID dst) argument
534 orl_im(int imm, const void* addr) argument
561 subl_ir(int imm, RegisterID dst) argument
572 subl_im(int imm, int offset, RegisterID base) argument
589 subq_ir(int imm, RegisterID dst) argument
600 subl_im(int imm, const void* addr) argument
627 xorl_im(int imm, int offset, RegisterID base) argument
638 xorl_ir(int imm, RegisterID dst) argument
655 xorq_ir(int imm, RegisterID dst) argument
667 sarl_i8r(int imm, RegisterID dst) argument
682 shrl_i8r(int imm, RegisterID dst) argument
697 shll_i8r(int imm, RegisterID dst) argument
718 sarq_i8r(int imm, RegisterID dst) argument
767 cmpl_ir(int imm, RegisterID dst) argument
778 cmpl_ir_force32(int imm, RegisterID dst) argument
784 cmpl_im(int imm, int offset, RegisterID base) argument
795 cmpb_im(int imm, int offset, RegisterID base) argument
801 cmpb_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
807 cmpl_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
818 cmpl_im_force32(int imm, int offset, RegisterID base) argument
840 cmpq_ir(int imm, RegisterID dst) argument
851 cmpq_im(int imm, int offset, RegisterID base) argument
862 cmpq_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
878 cmpl_im(int imm, const void* addr) argument
896 cmpw_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
914 testl_i32r(int imm, RegisterID dst) argument
920 testl_i32m(int imm, int offset, RegisterID base) argument
931 testb_im(int imm, int offset, RegisterID base) argument
937 testb_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
943 testl_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
955 testq_i32r(int imm, RegisterID dst) argument
961 testq_i32m(int imm, int offset, RegisterID base) argument
967 testq_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
980 testb_i8r(int imm, RegisterID dst) argument
1075 movl_i32r(int imm, RegisterID dst) argument
1081 movl_i32m(int imm, int offset, RegisterID base) argument
1145 movq_i32m(int imm, int offset, RegisterID base) argument
1151 movq_i64r(int64_t imm, RegisterID dst) argument
1180 movl_i32m(int imm, const void* addr) argument
1912 immediate8(int imm) argument
1917 immediate16(int imm) argument
1922 immediate32(int imm) argument
1927 immediate64(int64_t imm) argument
[all...]
H A DMacroAssemblerX86_64.h55 void add32(TrustedImm32 imm, AbsoluteAddress address) argument
58 add32(imm, Address(scratchRegister));
61 void and32(TrustedImm32 imm, AbsoluteAddress address) argument
64 and32(imm, Address(scratchRegister));
67 void or32(TrustedImm32 imm, AbsoluteAddress address) argument
70 or32(imm, Address(scratchRegister));
73 void sub32(TrustedImm32 imm, AbsoluteAddress address) argument
76 sub32(imm, Address(scratchRegister));
102 void convertInt32ToDouble(TrustedImm32 imm, FPRegisterID dest) argument
104 move(imm, scratchRegiste
108 store32(TrustedImm32 imm, void* address) argument
147 addPtr(TrustedImm32 imm, RegisterID srcDest) argument
152 addPtr(TrustedImmPtr imm, RegisterID dest) argument
158 addPtr(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
163 addPtr(TrustedImm32 imm, Address address) argument
168 addPtr(TrustedImm32 imm, AbsoluteAddress address) argument
179 andPtr(TrustedImm32 imm, RegisterID srcDest) argument
189 orPtr(TrustedImmPtr imm, RegisterID dest) argument
195 orPtr(TrustedImm32 imm, RegisterID dest) argument
212 orPtr(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
223 subPtr(TrustedImm32 imm, RegisterID dest) argument
228 subPtr(TrustedImmPtr imm, RegisterID dest) argument
239 xorPtr(TrustedImm32 imm, RegisterID srcDest) argument
293 storePtr(TrustedImmPtr imm, ImplicitAddress address) argument
411 branchSubPtr(Condition cond, TrustedImm32 imm, RegisterID dest) argument
[all...]
H A DMacroAssemblerMIPS.h107 void add32(TrustedImm32 imm, RegisterID dest) argument
109 add32(imm, dest, dest);
112 void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
114 if (!imm.m_isPointer && imm.m_value >= -32768 && imm.m_value <= 32767
117 addiu dest, src, imm
119 m_assembler.addiu(dest, src, imm.m_value);
122 li immTemp, imm
125 move(imm, immTempRegiste
130 add32(TrustedImm32 imm, Address address) argument
210 add32(TrustedImm32 imm, AbsoluteAddress address) argument
236 and32(TrustedImm32 imm, RegisterID dest) argument
253 lshift32(TrustedImm32 imm, RegisterID dest) argument
268 mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
299 or32(TrustedImm32 imm, RegisterID dest) argument
323 rshift32(TrustedImm32 imm, RegisterID dest) argument
333 urshift32(TrustedImm32 imm, RegisterID dest) argument
343 sub32(TrustedImm32 imm, RegisterID dest) argument
361 sub32(TrustedImm32 imm, Address address) argument
416 sub32(TrustedImm32 imm, AbsoluteAddress address) argument
444 xor32(TrustedImm32 imm, RegisterID dest) argument
722 store32(TrustedImm32 imm, ImplicitAddress address) argument
762 store32(TrustedImm32 imm, const void* address) argument
834 push(TrustedImm32 imm) argument
844 move(TrustedImm32 imm, RegisterID dest) argument
861 move(TrustedImmPtr imm, RegisterID dest) argument
1177 branchAdd32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1228 branchMul32(Condition cond, TrustedImm32 imm, RegisterID src, RegisterID dest) argument
1282 branchSub32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1466 moveWithPatch(TrustedImm32 imm, RegisterID dest) argument
[all...]
H A DMacroAssemblerX86.h55 void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
57 m_assembler.leal_mr(imm.m_value, src, dest);
60 void add32(TrustedImm32 imm, AbsoluteAddress address) argument
62 m_assembler.addl_im(imm.m_value, address.m_ptr);
65 void addWithCarry32(TrustedImm32 imm, AbsoluteAddress address) argument
67 m_assembler.adcl_im(imm.m_value, address.m_ptr);
70 void and32(TrustedImm32 imm, AbsoluteAddress address) argument
72 m_assembler.andl_im(imm.m_value, address.m_ptr);
75 void or32(TrustedImm32 imm, AbsoluteAddress address) argument
77 m_assembler.orl_im(imm
80 sub32(TrustedImm32 imm, AbsoluteAddress address) argument
101 store32(TrustedImm32 imm, void* address) argument
[all...]
H A DARMv7Assembler.h745 void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
751 ASSERT(imm.isValid());
754 if (!(rd & 8) && imm.isUInt10()) {
755 m_formatter.oneWordOp5Reg3Imm8(OP_ADD_SP_imm_T1, rd, imm.getUInt10() >> 2);
757 } else if ((rd == ARMRegisters::sp) && imm.isUInt9()) {
758 m_formatter.oneWordOp9Imm7(OP_ADD_SP_imm_T2, imm.getUInt9() >> 2);
762 if (imm.isUInt3()) {
763 m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, rd);
765 } else if ((rd == rn) && imm.isUInt8()) {
766 m_formatter.oneWordOp5Reg3Imm8(OP_ADD_imm_T2, rd, imm
802 add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
842 ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
912 bkpt(uint8_t imm=0) argument
924 cmn(RegisterID rn, ARMThumbImmediate imm) argument
932 cmp(RegisterID rn, ARMThumbImmediate imm) argument
959 eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1008 ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1068 ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1125 ldrb(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1203 movT3(RegisterID rd, ARMThumbImmediate imm) argument
1212 mov(RegisterID rd, ARMThumbImmediate imm) argument
1230 movt(RegisterID rd, ARMThumbImmediate imm) argument
1237 mvn(RegisterID rd, ARMThumbImmediate imm) argument
1266 orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1337 str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1397 sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1426 sub(RegisterID rd, ARMThumbImmediate imm, RegisterID rn) argument
1458 sub_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1501 tst(RegisterID rn, ARMThumbImmediate imm) argument
1556 vldr(FPDoubleRegisterID rd, RegisterID rn, int32_t imm) argument
1584 vstr(FPDoubleRegisterID rd, RegisterID rn, int32_t imm) argument
2179 twoWordOp5i6Imm4Reg4EncodedImmFirst(uint16_t op, ARMThumbImmediate imm) argument
2184 twoWordOp5i6Imm4Reg4EncodedImmSecond(uint16_t rd, ARMThumbImmediate imm) argument
2191 oneWordOp5Reg3Imm8(OpcodeID op, RegisterID rd, uint8_t imm) argument
2196 oneWordOp5Imm5Reg3Reg3(OpcodeID op, uint8_t imm, RegisterID reg1, RegisterID reg2) argument
2206 oneWordOp8Imm8(OpcodeID op, uint8_t imm) argument
2215 oneWordOp9Imm7(OpcodeID op, uint8_t imm) argument
2243 twoWordOp5i6Imm4Reg4EncodedImm(OpcodeID1 op, int imm4, RegisterID rd, ARMThumbImmediate imm) argument
2252 twoWordOp12Reg4Reg4Imm12(OpcodeID1 op, RegisterID reg1, RegisterID reg2, uint16_t imm) argument
2272 vfpMemOp(OpcodeID1 op1, OpcodeID2 op2, bool size, RegisterID rn, VFPOperand rd, int32_t imm) argument
[all...]
H A DMacroAssemblerARMv7.h151 void add32(TrustedImm32 imm, RegisterID dest) argument
153 add32(imm, dest, dest);
156 void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
158 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);
162 move(imm, dataTempRegister);
167 void add32(TrustedImm32 imm, Address address) argument
171 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);
177 move(imm, addressTempRegister);
190 void add32(TrustedImm32 imm, AbsoluteAddress address) argument
194 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm
212 and32(TrustedImm32 imm, RegisterID dest) argument
238 lshift32(TrustedImm32 imm, RegisterID dest) argument
248 mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
269 or32(TrustedImm32 imm, RegisterID dest) argument
290 rshift32(TrustedImm32 imm, RegisterID dest) argument
305 urshift32(TrustedImm32 imm, RegisterID dest) argument
315 sub32(TrustedImm32 imm, RegisterID dest) argument
326 sub32(TrustedImm32 imm, Address address) argument
349 sub32(TrustedImm32 imm, AbsoluteAddress address) argument
371 xor32(TrustedImm32 imm, RegisterID dest) argument
514 store32(TrustedImm32 imm, ImplicitAddress address) argument
526 store32(TrustedImm32 imm, const void* address) argument
751 push(TrustedImm32 imm) argument
761 move(TrustedImm32 imm, RegisterID dest) argument
787 move(TrustedImmPtr imm, RegisterID dest) argument
834 int32_t imm = right.m_value; local
852 int32_t imm = mask.m_value; local
1035 branchAdd32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1056 branchMul32(Condition cond, TrustedImm32 imm, RegisterID src, RegisterID dest) argument
1079 branchSub32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1199 moveWithPatch(TrustedImm32 imm, RegisterID dst) argument
1205 moveWithPatch(TrustedImmPtr imm, RegisterID dst) argument
1276 ARMThumbImmediate imm = ARMThumbImmediate::makeUInt12OrEncodedImm(address.offset); local
1323 moveFixedWidthEncoding(TrustedImm32 imm, RegisterID dst) argument
[all...]
H A DMacroAssemblerARM.h89 void add32(TrustedImm32 imm, Address address) argument
92 add32(imm, ARMRegisters::S1);
96 void add32(TrustedImm32 imm, RegisterID dest) argument
98 m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
112 void and32(TrustedImm32 imm, RegisterID dest) argument
114 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
130 void lshift32(TrustedImm32 imm, RegisterID dest) argument
132 m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
144 void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
146 move(imm, ARMRegister
165 or32(TrustedImm32 imm, RegisterID dest) argument
179 rshift32(TrustedImm32 imm, RegisterID dest) argument
193 urshift32(TrustedImm32 imm, RegisterID dest) argument
203 sub32(TrustedImm32 imm, RegisterID dest) argument
208 sub32(TrustedImm32 imm, Address address) argument
226 xor32(TrustedImm32 imm, RegisterID dest) argument
306 store32(TrustedImm32 imm, ImplicitAddress address) argument
321 store32(TrustedImm32 imm, void* address) argument
347 push(TrustedImm32 imm) argument
353 move(TrustedImm32 imm, RegisterID dest) argument
366 move(TrustedImmPtr imm, RegisterID dest) argument
522 branchAdd32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
551 branchMul32(Condition cond, TrustedImm32 imm, RegisterID src, RegisterID dest) argument
571 branchSub32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
679 add32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
684 add32(TrustedImm32 imm, AbsoluteAddress address) argument
693 sub32(TrustedImm32 imm, AbsoluteAddress address) argument
[all...]
H A DMacroAssemblerSH4.h96 void add32(TrustedImm32 imm, RegisterID dest) argument
98 if (m_assembler.isImmediate(imm.m_value)) {
99 m_assembler.addlImm8r(imm.m_value, dest);
104 m_assembler.loadConstant(imm.m_value, scr);
109 void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
113 add32(imm, dest);
116 void add32(TrustedImm32 imm, Address address) argument
120 add32(imm, scr);
138 void and32(TrustedImm32 imm, RegisterID dest) argument
140 if ((imm
156 rshift32(int imm, RegisterID dest) argument
164 lshift32(TrustedImm32 imm, RegisterID dest) argument
183 mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
203 or32(TrustedImm32 imm, RegisterID dest) argument
225 rshift32(TrustedImm32 imm, RegisterID dest) argument
236 sub32(TrustedImm32 imm, AbsoluteAddress address, RegisterID scratchReg) argument
254 sub32(TrustedImm32 imm, AbsoluteAddress address) argument
274 add32(TrustedImm32 imm, AbsoluteAddress address, RegisterID scratchReg) argument
292 add32(TrustedImm32 imm, AbsoluteAddress address) argument
312 sub32(TrustedImm32 imm, RegisterID dest) argument
338 xor32(TrustedImm32 imm, RegisterID srcDest) argument
351 compare32(int imm, RegisterID dst, Condition cond) argument
388 testImm(int imm, int offset, RegisterID base) argument
411 testlImm(int imm, RegisterID dst) argument
450 compare32(int imm, int offset, RegisterID base, Condition cond) argument
678 store32(TrustedImm32 imm, ImplicitAddress address) argument
700 store32(TrustedImm32 imm, void* address) argument
1174 push(TrustedImm32 imm) argument
1184 move(TrustedImm32 imm, RegisterID dest) argument
1201 move(TrustedImmPtr imm, RegisterID dest) argument
1493 branchAdd32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1535 branchMul32(Condition cond, TrustedImm32 imm, RegisterID src, RegisterID dest) argument
1570 branchSub32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1631 urshift32(TrustedImm32 imm, RegisterID dest) argument
[all...]
H A DMacroAssemblerX86Common.h95 void add32(TrustedImm32 imm, Address address) argument
97 m_assembler.addl_im(imm.m_value, address.offset, address.base);
100 void add32(TrustedImm32 imm, RegisterID dest) argument
102 m_assembler.addl_ir(imm.m_value, dest);
120 void and32(TrustedImm32 imm, RegisterID dest) argument
122 m_assembler.andl_ir(imm.m_value, dest);
135 void and32(TrustedImm32 imm, Address address) argument
137 m_assembler.andl_im(imm.m_value, address.offset, address.base);
152 void and32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
155 and32(imm, des
183 lshift32(TrustedImm32 imm, RegisterID dest) argument
188 lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) argument
205 mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
235 or32(TrustedImm32 imm, RegisterID dest) argument
250 or32(TrustedImm32 imm, Address address) argument
267 or32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
298 rshift32(TrustedImm32 imm, RegisterID dest) argument
303 rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) argument
335 urshift32(TrustedImm32 imm, RegisterID dest) argument
340 urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) argument
352 sub32(TrustedImm32 imm, RegisterID dest) argument
357 sub32(TrustedImm32 imm, Address address) argument
378 xor32(TrustedImm32 imm, Address dest) argument
383 xor32(TrustedImm32 imm, RegisterID dest) argument
410 xor32(TrustedImm32 imm, RegisterID src, RegisterID dest) argument
475 store32(TrustedImm32 imm, ImplicitAddress address) argument
699 push(TrustedImm32 imm) argument
709 move(TrustedImm32 imm, RegisterID dest) argument
728 move(TrustedImmPtr imm, RegisterID dest) argument
755 move(TrustedImmPtr imm, RegisterID dest) argument
971 branchAdd32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1007 branchAdd32(Condition cond, RegisterID src, TrustedImm32 imm, RegisterID dest) argument
1027 branchMul32(Condition cond, TrustedImm32 imm, RegisterID src, RegisterID dest) argument
1049 branchSub32(Condition cond, TrustedImm32 imm, RegisterID dest) argument
1056 branchSub32(Condition cond, TrustedImm32 imm, Address dest) argument
[all...]
H A DMIPSAssembler.h250 void li(RegisterID dest, int imm) argument
252 if (imm >= -32768 && imm <= 32767)
253 addiu(dest, MIPSRegisters::zero, imm);
254 else if (imm >= 0 && imm < 65536)
255 ori(dest, MIPSRegisters::zero, imm);
257 lui(dest, imm >> 16);
258 if (imm & 0xffff)
259 ori(dest, dest, imm);
263 lui(RegisterID rt, int imm) argument
268 addiu(RegisterID rt, RegisterID rs, int imm) argument
323 andi(RegisterID rt, RegisterID rs, int imm) argument
341 ori(RegisterID rt, RegisterID rs, int imm) argument
353 xori(RegisterID rt, RegisterID rs, int imm) argument
371 sltiu(RegisterID rt, RegisterID rs, int imm) argument
475 bgez(RegisterID rs, int imm) argument
480 bltz(RegisterID rs, int imm) argument
485 beq(RegisterID rs, RegisterID rt, int imm) argument
490 bne(RegisterID rs, RegisterID rt, int imm) argument
[all...]
H A DARMAssembler.h480 void ldr_imm(int rd, ARMWord imm, Condition cc = AL) argument
482 m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true); local
485 void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL) argument
487 m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm); local
741 // Must be an ldr ..., [pc +/- imm]
752 // Must be an ldr ..., [pc +/- imm]
857 static ARMWord getOp2Byte(ARMWord imm) argument
859 ASSERT(imm <= 0xff);
860 return OP2_IMMh | (imm & 0x0f) | ((imm
866 getImm16Op2(ARMWord imm) argument
877 getOffsetForHalfwordDataTransfer(ARMWord imm, int tmpReg) argument
[all...]
/external/openssl/crypto/perlasm/
H A Dx86asm.pl87 { my($dst,$src,$imm)=@_;
89 { &::data_byte(0x66,0x0f,0x3a,0x16,0xc0|($2<<3)|$regrm{$1},$imm); }
95 { my($dst,$src,$imm)=@_;
97 { &::data_byte(0x66,0x0f,0x3a,0x22,0xc0|($1<<3)|$regrm{$2},$imm); }
111 { my($dst,$src,$imm)=@_;
113 { &::data_byte(0x66,0x0f,0x3a,0x0f,0xc0|($1<<3)|$2,$imm); }
119 { my($dst,$src,$imm)=@_;
121 { &::data_byte(0x66,0x0f,0x3a,0x44,0xc0|($1<<3)|$2,$imm); }
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0;
129 if (isIntS32Immediate(N.getOperand(1), imm))
145 /// a signed 32-bit displacement [r+imm], and if it is not better
154 int32_t imm = 0; local
155 if (isIntS32Immediate(N.getOperand(1), imm)) {
156 Disp = CurDAG->getTargetConstant(imm, MVT::i32);
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
[all...]
/external/v8/src/arm/
H A Dconstants-arm.cc52 uint64_t imm = high16 << 48; local
54 memcpy(&d, &imm, 8);
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1122 uint32_t imm = Val & 0xFF; local
1124 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1135 unsigned imm = fieldFromInstruction(Val, 7, 5); local
1157 if (Shift == ARM_AM::ror && imm == 0)
1160 unsigned Op = Shift | (imm << 3);
1300 unsigned imm = fieldFromInstruction(Insn, 0, 8); local
1382 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1383 Inst.addOperand(MCOperand::CreateImm(imm));
1445 unsigned imm = fieldFromInstruction(Insn, 0, 12); local
1526 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); local
1548 unsigned imm = fieldFromInstruction(Val, 7, 5); local
1590 unsigned imm = fieldFromInstruction(Insn, 8, 4); local
1972 unsigned imm = 0; local
1997 unsigned imm = 0; local
2050 unsigned imm = fieldFromInstruction(Val, 0, 12); local
2071 unsigned imm = fieldFromInstruction(Val, 0, 8); local
2093 unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) | local
2110 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; local
2884 unsigned imm = fieldFromInstruction(Insn, 0, 4); local
3007 unsigned imm = fieldFromInstruction(Insn, 0, 8); local
3070 unsigned imm = fieldFromInstruction(Val, 3, 5); local
3081 unsigned imm = Val << 2; local
3103 unsigned imm = fieldFromInstruction(Val, 0, 2); local
3153 int imm = fieldFromInstruction(Insn, 0, 12); local
3174 int imm = Val & 0xFF; local
3188 unsigned imm = fieldFromInstruction(Val, 0, 9); local
3203 unsigned imm = fieldFromInstruction(Val, 0, 8); local
3215 int imm = Val & 0xFF; local
3231 unsigned imm = fieldFromInstruction(Val, 0, 9); local
3292 unsigned imm = fieldFromInstruction(Val, 0, 12); local
3304 unsigned imm = fieldFromInstruction(Insn, 0, 7); local
3433 unsigned imm = fieldFromInstruction(Insn, 0, 4); local
3459 unsigned imm = fieldFromInstruction(Val, 0, 8); local
3478 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); local
3589 unsigned imm = fieldFromInstruction(Insn, 0, 12); local
3614 unsigned imm = fieldFromInstruction(Insn, 0, 12); local
3642 unsigned imm = fieldFromInstruction(Insn, 0, 12); local
3667 unsigned imm = fieldFromInstruction(Insn, 0, 12); local
4441 unsigned imm = fieldFromInstruction(Insn, 16, 6); local
4469 unsigned imm = fieldFromInstruction(Insn, 16, 6); local
[all...]
/external/qemu/distrib/sdl-1.2.15/src/video/
H A Dmmx.h240 #define mmx_i2r(op, imm, reg) \
243 mmx_trace.uq = (imm); \
244 printf(#op "_i2r(" #imm "=0x%08x%08x, ", \
253 : "y" (imm)); \
346 #define mmx_i2r(op, imm, reg) \
349 : "y" (imm) )
582 #define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
587 #define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, re
[all...]
/external/v8/src/mips/
H A Ddisasm-mips.cc256 int32_t imm = instr->Imm16Value(); local
257 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
263 int32_t imm = ((instr->Imm16Value()) << 16) >> 16; local
264 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
270 int32_t imm = instr->Imm16Value(); local
271 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
277 uint32_t imm = instr->Imm26Value() << kImmFieldShift; local
278 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
/external/qemu/
H A Darm-dis.c1776 int imm; local
1778 imm = (given & 0xf) | ((given & 0xe0) >> 1);
1780 /* Is ``imm'' a negative number? */
1781 if (imm & 0x40)
1782 imm |= (-1 << 7);
1784 func (stream, "%d", imm);
2985 int imm; local
2987 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
2988 func (stream, "%d", imm);
3179 long imm local
3369 unsigned int bits = 0, imm, imm8, mod; local
3392 unsigned int imm = 0; local
3403 unsigned int imm = 0; local
3415 unsigned int imm = 0; local
[all...]
/external/clang/lib/Headers/
H A Davx2intrin.h468 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \
471 (imm) & 0x3, ((imm) & 0xc) >> 2, \
472 ((imm) & 0x30) >> 4, ((imm) & 0xc0) >> 6, \
473 4 + (((imm) & 0x03) >> 0), \
474 4 + (((imm) & 0x0c) >> 2), \
475 4 + (((imm) & 0x30) >> 4), \
476 4 + (((imm) & 0xc0) >> 6)); })
478 #define _mm256_shufflehi_epi16(a, imm) __extension_
[all...]
/external/clang/lib/include/
H A Davx2intrin.h468 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \
471 (imm) & 0x3, ((imm) & 0xc) >> 2, \
472 ((imm) & 0x30) >> 4, ((imm) & 0xc0) >> 6, \
473 4 + (((imm) & 0x03) >> 0), \
474 4 + (((imm) & 0x0c) >> 2), \
475 4 + (((imm) & 0x30) >> 4), \
476 4 + (((imm) & 0xc0) >> 6)); })
478 #define _mm256_shufflehi_epi16(a, imm) __extension_
[all...]
/external/valgrind/main/VEX/priv/
H A Dguest_arm_toIR.c2293 UInt imm = (insn_11_0 >> 0) & 0xFF; local
2296 imm = ROR32(imm, rot);
2301 assign( *shco, mkU32( (imm >> 31) & 1 ) );
2304 DIS(buf, "#0x%x", imm);
2305 assign( *shop, mkU32(imm) );
2877 ULong imm; local
2896 imm = 8;
2897 imm = (imm <<
3036 ULong imm = 0; local
3448 ULong imm = 0; local
3817 ULong imm; local
3954 ULong esize, imm; local
4485 ULong imm; local
4521 ULong imm; local
4806 ULong imm; local
5400 ULong imm; local
5615 ULong imm; local
5680 ULong imm; local
5780 ULong imm; local
5896 ULong imm = 0; local
7564 ppNeonImm(UInt imm, UInt cmode, UInt op) argument
7626 DIPimm(UInt imm, UInt cmode, UInt op, const char *instr, UInt Q, UInt dreg) argument
7646 ULong imm = 0; local
10987 UInt imm; local
11003 ULong imm; local
13313 UInt imm = (INSN(11,0) >> 0) & 0xFF; local
[all...]
/external/qemu/target-arm/
H A Dtranslate.c4427 uint32_t imm, mask; local
4876 imm = (uint8_t) shift;
4877 imm |= imm << 8;
4878 imm |= imm << 16;
4881 imm = (uint16_t) shift;
4882 imm |= imm << 16;
4886 imm
7781 uint32_t insn, imm, shift, offset; local
[all...]
/external/llvm/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeMCCodeEmitter.cpp86 void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const;
124 EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const { argument
125 int32_t val = (int32_t)imm.getImm();

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