1405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham/*	$OpenBSD: regdef.h,v 1.3 2005/08/07 07:29:44 miod Exp $	*/
2405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham
3405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham/*
4405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * Copyright (c) 1992, 1993
5405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *	The Regents of the University of California.  All rights reserved.
6405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *
7405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * This code is derived from software contributed to Berkeley by
8405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * Ralph Campbell. This file is derived from the MIPS RISC
9405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * Architecture book by Gerry Kane.
10405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *
11405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * Redistribution and use in source and binary forms, with or without
12405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * modification, are permitted provided that the following conditions
13405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * are met:
14405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * 1. Redistributions of source code must retain the above copyright
15405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *    notice, this list of conditions and the following disclaimer.
16405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * 2. Redistributions in binary form must reproduce the above copyright
17405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *    notice, this list of conditions and the following disclaimer in the
18405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *    documentation and/or other materials provided with the distribution.
19405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * 3. Neither the name of the University nor the names of its contributors
20405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *    may be used to endorse or promote products derived from this software
21405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *    without specific prior written permission.
22405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *
23405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham * SUCH DAMAGE.
34405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *
35405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham *	@(#)regdef.h	8.1 (Berkeley) 6/10/93
36405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham */
37405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#ifndef _MIPS_REGDEF_H_
38405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define _MIPS_REGDEF_H_
39405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham
40405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define zero	$0	/* always zero */
41405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define AT	$at	/* assembler temp */
42405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define v0	$2	/* return value */
43405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define v1	$3
44405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a0	$4	/* argument registers */
45405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a1	$5
46405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a2	$6
47405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a3	$7
48405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#if defined(__mips_n32) || defined(__mips_n64)
49405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a4	$8	/* expanded register arguments */
50405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a5	$9
51405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a6	$10
52405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define a7	$11
53405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta0	$8	/* alias */
54405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta1	$9
55405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta2	$10
56405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta3	$11
57405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t0	$12	/* temp registers (not saved across subroutine calls) */
58405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t1	$13
59405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t2	$14
60405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t3	$15
61405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#else
62405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t0	$8	/* temp registers (not saved across subroutine calls) */
63405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t1	$9
64405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t2	$10
65405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t3	$11
66405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t4	$12
67405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t5	$13
68405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t6	$14
69405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t7	$15
70405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta0	$12	/* alias */
71405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta1	$13
72405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta2	$14
73405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ta3	$15
74405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#endif
75405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s0	$16	/* saved across subroutine calls (callee saved) */
76405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s1	$17
77405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s2	$18
78405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s3	$19
79405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s4	$20
80405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s5	$21
81405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s6	$22
82405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s7	$23
83405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t8	$24	/* two more temp registers */
84405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define t9	$25
85405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define k0	$26	/* kernel temporary */
86405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define k1	$27
87405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define gp	$28	/* global pointer */
88405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define sp	$29	/* stack pointer */
89405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define s8	$30	/* one more callee saved */
90405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#define ra	$31	/* return address */
91405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham
92405b8029a6888f386adf3512113a33546141d1c8Raghu Gandham#endif /* !_MIPS_REGDEF_H_ */
93